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| 1 MB86290A graphics controller hardware specifications revision 2.0b 23 may 2000 copyright ? fujitsu limited 1998, 1999 all rights reserved
2 all rights reserved the information in this document has been carefully checked and is believed to be reliable. however, fujitsu limited assumes no responsibility for inaccuracies. the information in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by fujitsu limited, or its subsidiaries. fujitsu limited reserves the right to change products or specifications without notice. no part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of fujitsu limited. 3 1 overview...................................................................................................................... ...........7 1.1 introduction ................................................................................................................ .....7 1.2 system configuration .....................................................................................................8 1.3 outline ..................................................................................................................... .......9 1.4 block diagram ..............................................................................................................1 0 1.5 functional overview ..................................................................................................... 11 1.5.1 system configuration .................................................................................................... .... 11 1.5.2 display controller ...................................................................................................... ........12 1.5.3 frame control ........................................................................................................... .........13 1.5.4 2d drawing .............................................................................................................. ..........14 1.5.5 3d drawing .............................................................................................................. ..........16 1.5.6 special effects ......................................................................................................... ..........17 1.5.7 display list............................................................................................................ .............19 2 signal pins................................................................................................................... .........20 2.1 signals ..................................................................................................................... .....20 2.1.1 signals ................................................................................................................. ..............20 2.2 pin assignment.............................................................................................................2 1 2.2.1 pin assignment diagram .................................................................................................. .21 2.2.2 pin assignment table .................................................................................................... ....22 2.3 signal descriptions .......................................................................................................24 2.3.1 host cpu interface...................................................................................................... ......24 2.3.2 video interface......................................................................................................... ..........26 2.3.3 graphics memory interface ............................................................................................... 28 2.3.4 clock input ............................................................................................................. ............29 3 host interface ................................................................................................................ .......30 3.1 operation mode ............................................................................................................30 3.1.1 host cpu mode ........................................................................................................... ......30 3.1.2 endian.................................................................................................................. ..............30 3.2 access mode ................................................................................................................3 1 3.2.1 sram interface .......................................................................................................... .......31 3.2.2 fifo interface.......................................................................................................... ..........31 3.3 dma transfer ...............................................................................................................3 2 3.3.1 data transfer unit...................................................................................................... ........32 3.3.2 address mode............................................................................................................ ........32 3.3.3 bus mode................................................................................................................ ...........33 3.3.4 dma transfer request .................................................................................................... ..33 3.3.5 ending dma transfer ..................................................................................................... ...34 3.4 interrupt request ..........................................................................................................3 5 3.5 transfer of local display list .......................................................................................36 3.6 memory map.................................................................................................................3 7 4 graphics memory ............................................................................................................... ..38 4.1 configuration ............................................................................................................... .38 4.1.1 data type............................................................................................................... ............38 4.1.2 memory layout ........................................................................................................... .......39 4.1.3 memory data format...................................................................................................... ...40 4 4.2 frame management .....................................................................................................42 4.2.1 single buffer ........................................................................................................... ...........42 4.2.2 double buffer ........................................................................................................... ..........42 4.3 memory access ............................................................................................................43 4.3.1 memory access by host cpu ...........................................................................................43 4.3.2 priority of memory access ............................................................................................... ..43 5 display controller ............................................................................................................ .....44 5.1 overview.................................................................................................................... ...44 5.2 display function ...........................................................................................................4 5 5.2.1 layer configuration ..................................................................................................... ......45 5.2.2 overlay................................................................................................................. ..............46 5.2.3 display parameters ...................................................................................................... .....47 5.2.4 display position control................................................................................................ .....48 5.3 display color ............................................................................................................... .50 5.3.1 color look-up table..................................................................................................... ......50 5.3.2 chroma-key operation .................................................................................................... ..50 5.4 cursor ...................................................................................................................... .....51 5.4.1 cursor display function ................................................................................................. ...51 5.4.2 cursor management ....................................................................................................... ...51 5.5 processing flow for display data.................................................................................52 5.6 synchronization control ...............................................................................................54 5.6.1 applicable display resolution ........................................................................................... 54 5.6.2 interlace display ....................................................................................................... .........54 5.6.3 external synchronization ................................................................................................ ...55 5.7 video interface............................................................................................................. .58 5.7.1 ntsc output ............................................................................................................. ........58 6 drawing control ............................................................................................................... .....59 6.1 coordinates ................................................................................................................. .59 6.1.1 drawing coordinate ...................................................................................................... .....59 6.1.2 texture coordinate ...................................................................................................... ......60 6.1.3 frame buffer ............................................................................................................ ..........61 6.2 polygon drawing...........................................................................................................62 6.2.1 drawing primitives ...................................................................................................... .......62 6.2.2 polygon drawing......................................................................................................... .......62 6.2.3 drawing parameters ...................................................................................................... ....63 6.2.4 anti-aliasing function .................................................................................................. ......64 6.3 bit map operation.........................................................................................................65 6.3.1 blt..................................................................................................................... ................65 6.3.2 pattern data format ..................................................................................................... .....65 6.4 texture mapping ...........................................................................................................66 6.4.1 texture size ............................................................................................................ ...........66 6.4.2 texture memory .......................................................................................................... .......66 6.4.3 texture lapping ......................................................................................................... ........67 6.4.4 filtering ............................................................................................................... ...............68 6.4.5 perspective correction .................................................................................................. ....69 6.4.6 texture blending ........................................................................................................ ........69 6.5 rendering ................................................................................................................... ..70 5 6.5.1 tiling.................................................................................................................. .................70 6.5.2 alpha blending.......................................................................................................... .........71 6.5.3 logical calculation..................................................................................................... ........71 6.5.4 hidden surface management ............................................................................................72 6.6 drawing attributes ........................................................................................................73 6.6.1 line draw attributes .................................................................................................... ......73 6.6.2 triangle draw attributes ................................................................................................ ....73 6.6.3 texture attributes ...................................................................................................... .........74 6.6.4 character/font drawing and blt attributes ......................................................................74 6.7 display list ................................................................................................................ ...75 6.7.1 overview ................................................................................................................ ............75 6.7.2 header format........................................................................................................... ........76 6.7.3 display list command overview.......................................................................................77 6.7.4 details of display list commands .....................................................................................81 7 registers..................................................................................................................... ..........93 7.1 description................................................................................................................. ...93 7.1.1 host interface registers ................................................................................................ ....94 7.1.2 graphics memory interface registers ...............................................................................98 7.1.3 display control register ................................................................................................ ..101 7.1.4 draw control registers.................................................................................................. ..124 7.1.5 draw mode parameter registers ....................................................................................127 7.1.6 triangle draw registers ................................................................................................. .141 7.1.7 line draw registers ..................................................................................................... ...144 7.1.8 pixel plot registers.................................................................................................... ......145 7.1.9 rectangle draw registers ...............................................................................................1 46 7.1.10 blt registers.......................................................................................................... .........147 7.1.11 fast2dline draw registers ...........................................................................................148 7.1.12 fast2dtriangle draw registers.....................................................................................149 7.1.12 displaylist fifo registers ............................................................................................1 49 8 timing diagram ................................................................................................................ ..150 8.1 host interface .............................................................................................................1 50 8.1.1 cpu read/write timing diagram for sh3 mode ........................................................................150 8.1.2 cpu read/write timing diagram for sh4 mode ........................................................................151 8.1.3 cpu read/write timing diagram in v832 mode ........................................................................152 8.1.4 sh4 single-address dma write (transfer of 1 long word)........................................................153 8.1.5 sh4 single-address dma write (transfer of 8 long words)......................................................154 8.1.6 sh3/4 dual-address dma (transfer of 1 long word).................................................................155 8.1.7 sh3/4 dual-address dma (transfer of 8 long words) ..............................................................156 8.1.8 v832 dma transfer ....................................................................................................... ..157 sh4 single-address dma transfer end timing ........................................................................158 8.1.10 sh3/4 dual-address dma transfer end timing............................................................159 8.1.11 v832 dma transfer end timing ....................................................................................160 8.2 graphics memory interface ........................................................................................161 8.2.1 timing of read access to same row address ...............................................................161 8.2.2 timing of read access to different row addresses .......................................................162 8.2.3 timing of write access to same row address ...............................................................163 8.2.4 timing of write access to different row addresses .......................................................164 6 8.2.5 timing of read/write access to same row address......................................................165 8.2.6 delay between actv commands ...................................................................................166 8.2.7 delay between refresh command and next actv command......................................167 8.3 display timing ............................................................................................................16 8 8.3.1 non-interlaced video mode .............................................................................................16 8 8.3.2 interlaced video mode ................................................................................................... ..169 8.4 cpu cautions .............................................................................................................170 8.5 sh3 mode...................................................................................................................1 70 8.6 sh4 mode...................................................................................................................1 71 8.7 v832 mode .................................................................................................................17 1 8.8 dma transfer modes supported by sh3, sh4, and v832 ........................................171 9 electrical characteristics (preliminary target specifications) ............................................172 9.1 absolute maximum ratings........................................................................................172 9.2 recommended operating conditions ........................................................................173 9.2.1 recommended operating conditions .............................................................................173 9.2.2 power-on precautions .................................................................................................... .173 9.3 dc characteristics......................................................................................................174 9.4 ac characteristics ........................................................................................................ ..175 9.4.1 host interface............................................................................................................ ..............175 9.4.2 video interface ........................................................................................................... .............176 9.4.3 graphics memory interface................................................................................................. ....177 9.4.4 pll specifications........................................................................................................ ...........177 9.5 timing diagram ..........................................................................................................178 9.5.1 host interface.......................................................................................................... .........178 9.5.2 video interface......................................................................................................... ........181 9.5.3 graphics memory interface .............................................................................................18 3 7 1 overview 1.1 introduction recent consumer information processing systems, such as car navigation systems, require graphics capabilities for web page browsing and 3d object manipulation. the required performance level for these graphics operations is also increasing. this MB86290A graphics controller provides an optimized solution for these new requirements. target applications car navigation systems consumer information processing systems including digital stb mobile ip terminals (windows ce hpc/ppc) consumer or arcade game machines 8 1.2 system configuration the following figure shows an example of a car navigation system using MB86290A. system configuration MB86290A graphics controller monitor (lcd/crt) sdram main cpu system bus rgb cache irc timer uart dram dmac flash adpcm speaker pcmcia i/f dvd drive unit pc card audio codec gps unit gyro sensor unit vics unit mic video i/f video dvd decoder 9 1.3 outline high performance the maximum operating frequency is 100 mhz. at this speed, the pixel fill rate is 100 mpixels/sec (2d drawing without special effects). flexible display controller display resolutions up to xga (1024 768) and on-chip dac are supported. the full screen can be split into two separate parts (left/right) each displaying different contents simultaneously. smooth double-buffer-mode animation is supported. each part of the screen can be scrolled independently. in addition, up to three screen layers can be overlaid. alpha blending for transparent display of lower-layer contents is also supported. this function can be used to blend a navigation map onto a text window. 2d rendering anti-aliasing and alpha blending are supported to display high-quality graphics on low-resolution monitors. 3d rendering professional 3d rendering features, including perspective texture mapping, gouraud shading, etc., are supported. others cmos 0.25-m technology hqfp240 package (lead pitch 0.5 mm) supply voltage 2.5 v (internal)/3.3 v (i/o) 10 1.4 block diagram the MB86290A block diagram is shown below: MB86290A block diagram memory control host interface draw engine p re-processor dda blender z color texture pattern display control host-bus pixel-bus cursor sync pll color lut d/ a blender fifo fifo 11 1.5 functional overview 1.5.1 system configuration host cpu interface MB86290A can be connected to hitachis sh3 or sh4 cpus and necs v832 cpu without any glue logic. the host MB86290A cpu interface can drive the host cpu dmac and transfer all graphical source data (display list, texture patterns, etc.) from the host (main) memory to its internal registers (or external frame memory). graphics memory synchronous dram is attached externally. either the 32-bit or 64-bit mode is supported as the interface with these external sdram devices. the external sdram operation frequency is the same as MB86290A (up to 100 mhz). applicable memory device configurations are as follows: graphics memory device configuration type data bus width # of devices total capacity sdram 64 mbit (x32 bit) 32 bit 1 8 mb sdram 64 mbit (x32 bit) 64 bit 2 16 mb sdram 64 mbit (x16bit) 64 bit 4 32 mb display signals MB86290A has three channels of 8-bit d/a converters and outputs analog rgb signals. superimposing is possible by applying an external sync signal. 12 1.5.2 display controller screen resolution various resolutions are achieved by using a programmable timing generator as follows: screen resolutions resolution 1024 768 1024 600 800 600 854 480 640 480 480 234 400 234 320 234 display colors there are two pixel color modes (indirect and direct). in the indirect mode, each pixel is expressed in 8-bit code. the actual display color is referenced using a color look-up table (color pallet). in this mode, each color of the look- up table is represented as 17 bits (rgb 6 bits each and independent alpha- blend bit), and 256 colors are selected from 262,144 colors. in the direct mode, each pixel is expressed as 16-bit code (rgb 5 bits each and reserved intensity bit). in this mode, 32,768 colors can be displayed. tv/video display MB86290A can output a graphics image synchronized with external tv/video display signals. the graphics image can be overlapped at any area on the tv/video display window. MB86290A outputs a control signal to switch the display window externally. this scheme supports both interlace and non-interlace. overlay up to three extra layers can be overlaid on the base window. when multiple layers are overlaid, the lower layer image can be displayed according to the setting of the transparency option. any codes in the color pallet can be assigned a transparent color. code 0 in the indirect mode or color value 0 in the direct mode sets this transparent option. 13 hardware cursor MB86290A supports two separate hardware cursor functions. each of these hardware cursors is specified as a 64 64-pixel area. each pixel of these hardware cursors is 8 bits and uses the indirect mode look-up table. 1.5.3 frame control double buffer scheme this mode provides smooth animation. the display frame and drawing frame are switched back and forth at each scan frame. a program in the vertical blanking period controls flipping. scroll scheme wrap around scrolling can be done by setting the drawing area, display area, display size and start address independently. windows display the whole screen can be split into two vertically separate windows. both windows can be controlled independently. 14 1.5.4 2d drawing 2d primitives MB86290A provides automatic drawing of various primitives and patterns (drawing surfaces) to frame memory in either indirect color (8 bits/pixel referencing appropriate palette) or direct color (16 bits/pixel) mode. alpha blending and anti-aliasing features are useful when the direct color mode is selected. a triangle is drawn in a single color, mapped with a style image formed by a single color or 2d pattern (tiling), or mapped with a texture pattern by designating coordinates of the 2d pattern at each vertex (texture mapping). alpha blending can be applied either per entire shape in single color mode or per pixel in tiling/texture mapping mode. when an object is drawn in single color or filled with a 2d pattern (without using gouraud shading or texture mapping), dedicated primitives, such as fast2dline and fast2dtriangle, are used. only vertex coordinates are set for these primitives. fast2dtriangle is also used to draw polygons. 2d primitives primitive type description point plots point line draws line triangle draws triangle fast2dline draws lines the number of parameters set for this primitive is less than that for line. the cpu load to use this primitive is lighter than using line. fast2dtriangle draws triangles. when a triangle is drawn in one color or filled with a 2d pattern, the cpu load to apply this primitive is lighter than using triangle. polygon draw this function draws various random shapes formed using multiple vertices. there is no restriction on the number of vertices number, however, if any sides forming the random shape cross each other, the shape is unsupported. the polygon draw flag buffer must be defined in graphics memory as a work field to draw random shapes. 15 blt/rectangle fill this function draws a rectangle using logical calculations. it is used to clear the frame memory and z buffer. at scrolling, the rolled over part can be cleared by using this function in the blanking time period. blt attributes attribute description raster operation selects two source logical operation mode pattern (text) drawing this function draws a binary pattern (text) in a designated color. pattern (text) drawing attributes attribute description enlarge 2 2 horizontally 2 shrink horizontally 1/2 1/2 1/2 clipping this function sets a rectangular window in a frame memory drawing surface and disables drawing of anything outside that window. 16 1.5.5 3d drawing 3d primitives this function draws 3d objects in frame memory in the direct color mode. 3d primitives primitive description point plots 3d point line draws 3d line triangle draws 3d triangle 3d drawing attributes MB86290Ahas various professional 3d graphics features, including gouraud shading and texture mapping with bi-linear filtering/automatic perspective correction, and provides high- quality realistic 3d drawing. a built-in sophisticated texture mapping unit delivers fast pixel calculations. this unit also delivers color blending between the shading color and texture color as well as alpha blending per pixel. hidden surface management MB86290A supports the z buffer for hidden surface management. 17 1.5.6 special effects anti-aliasing anti-aliasing manipulates lines and borders of polygons in sub-pixel units to eliminate jaggies on bias lines. it is used as a functional option for 2d drawing (in direct color mode only). line drawing this function draws lines of a specific width. detecting a line pattern can also draw a broken line. the anti-aliasing feature is also useful to draw smooth lines. line draw attributes attribute description width selectable from 1 to 32 pixels broken line set by 32 bit of broken line pattern alpha blending alpha blending blends two separate colors to provide a transparency effect. MB86290A supports two types of alpha blending; blending two different colors at drawing, and blending overlay planes at display. transparent color is not used for these blending options. alpha blending type description drawing - transparent ratio set in particular register - while one primitive (polygon, pattern, etc.), being drawn, registered transparent ratio applied overlay display - blends top layer pixel color and lower layer pixel at same position - transparent ratio set in particular register - registered transparent ratio applied during one frame scan shading gouraud shading is supported in the direct color mode to provide realistic 3d objects and color gradation. 18 texture mapping MB86290A supports texture mapping to map a style pattern onto the surface of 3d polygons. perspective correction is calculated automatically. for 2d pattern texture mapping, MB86290A has a built-in buffer memory for a field of up to 64 64 pixels. texture mapping is performed at high speeds while texture patterns are stored in this buffer. the texture pattern can also be stored in the graphics memory. in this case, a large pattern of up to 256 256 pixels can be used. texture mapping function description texture filtering - point sample - bi-linear filter texture coordinate correction - linear - perspective texture blending - decal - modulate - stencil texture alpha blending - normal - stencil - stencil alpha texture wrap - repeat - cramp 19 1.5.7 display list MB86290A is operated by feeding display lists which consists of a set of display commands, arguments and pattern data for them. normally, these display lists are stored either in off- screen frame memory (part of MB86290As local buffer) or host (main) memory that the dmac of the host cpu can access directly. MB86290A reads these display lists, decodes the commands, and executes them after reading all the necessary arguments. by executing this operation set until the end of the display list, all graphics operations, including image/object drawing and display control, are separated from the cpu. of course, the cpu program can also feed the display list information directly to MB86290As designated registers. 20 2 signal pins 2.1 signals 2.1.1 signals MB86290A signals d0-31 a2-24 bclki xrese t xcs xrd xwe0-3 xrd y xbs dreq drack dtack mode0-1 test0-5 md0-63 ma0-13 mras mcas mwe mdqm0-7 MB86290A graphics controller graphics memory interface dclko dckli aoutr,g,b hsync vsync eo gv video interface host cpu interface hqfp240 mclko mclki mcke xin t csync acompr,g,b clk s vref vro clock input ckm 21 2.2 pin assignment 2.2.1 pin assignment diagram MB86290A pin assignment test4 mode1 mode0 dclki vddl vss vddh dclko hsync vsync csync gv eo avs4 aoutr avd4 vro vref acomp r avs3 avd3 avs2 aoutg avd2 acomp g acomp b avd1 aoutb avs1 22 2.2.2 pin assignment table no. pin name no. pin name no. pin name no. pin name 1 xint 61 md14 121 md32 181 a2 2 dreq 62 md15 122 md33 182 a3 3 xrdy 63 md16 123 md34 183 a4 4 d0 64 md17 124 md35 184 a5 5 d1 65 vddh 125 md36 185 a6 6 d2 66 vss 126 md37 186 a7 7 d3 67 vddl 127 md38 187 vss 8 d4 68 md18 128 md39 188 vddl 9 d5 69 md19 129 md40 189 a8 10 d6 70 md20 130 md41 190 a9 11 d7 71 md21 131 vddh 191 a10 12 d8 72 md22 132 vss 192 a11 13 d9 73 md23 133 vddl 193 a12 14 vddh 74 md24 134 md42 194 a13 15 vss 75 vss 135 md43 195 a14 16 vddl 76 md25 136 md44 196 a15 17 d10 77 md26 137 md45 197 a16 18 d11 78 md27 138 md46 198 a17 19 d12 79 md28 139 md47 199 vss 20 d13 80 md29 140 md48 200 vddl 21 d14 81 md30 141 md49 201 a18 22 d15 82 md31 142 vss 202 a19 23 d16 83 vddh 143 md50 203 a20 24 vss 84 vss 144 md51 204 a21 25 d17 85 vddl 145 md52 205 a22 26 d18 86 dqm0 146 md53 206 a23 27 d19 87 dqm1 147 md54 207 vss 28 d20 88 dqm2 148 md55 208 a24 29 d21 89 dqm3 149 md56 209 ckm 30 d22 90 mras 150 vddh 210 test3 31 vddh 91 mcas 151 vss 211 23 vss/avs: ground vddh: 3.3-v power supply vddl: 2.5-v power supply avd: 2.5-v analog power supply avd(vco): 2.5-v pll power supply note 1: do not connect anything to pin 211 24 2.3 signal descriptions 2.3.1 host cpu interface host cpu interface signals signal name i/o description mode0-1 input host cpu mode selection xreset input hardware reset d0-31 in/out host cpu bus data a2-a24 input host cpu bus address (in the v832 mode, a[24] is connected to xmwr.) bclki input host cpu bus clock xbs input bus cycle start xcs input chip select xrd input read strobe xwe0 input write strobe for d0-d7 xwe1 input write strobe for d8-d15 xwe2 input write strobe for d16-d23 xwe3 input write strobe for d24-d31 xrdy output tri-state wait request signal (in the sh3 mode, when this signal is 0, it indicates the wait state; in the sh4 and v832 modes, when this signal is 1, it indicates the wait state.) dreq output dma request signal (this signal is low-active in both the sh mode and v832 mode.) drack/dmaak input acknowledge signal issued in response to dma request (dmaak is used in the v832 mode; this signal is high-active in both the sh mode and v832 mode.) dtack/xtc input dma transfer strobe signal (xtc is used in the v832 mode. in the sh mode, this signal is high-active; in the v832 mode, it is low-active.) xint output interrupt signal issued to host cpu (in the sh mode, this signal is low-active; in the v832 mode, it is high- active) test0-5 input test signals 25 MB86290A can be connected to the hitachi sh4 (sh7750), sh3 (sh7709/09a) and nec v832. in the sram interface mode, MB86290A can be used with any other cpu as well. the host cpu is specified by the mode pins. mode 1 mode 2 cpu ll sh3 lh sh4 hl v832 hh reserved the host interface data bus is 32-bits wide (fixed). the address bus is 24-bits wide (per double word), and has a 32- mbyte address field. MB86290A uses a 32-mbyte address field. the external bus frequency is up to 100 mhz. in the sh4 mode and v832 mode, when the xrdy signal is low, it is in the ready state. in the sh3 mode, when the xrdy signal is low, it is in the wait state. dma data transfer is supported using an external dmac. an interrupt request signal is generated to the host cpu. the xreset input must be kept low (active) for at least 300 s after setting the s (pll reset) signal to high. test signals must be clamped to high level. in the v832 mode, MB86290A signals are connected to the v832 cpu as follows: MB86290A signal pins v832 signal pins a24 xmwr dtack xtc drack dmaak 26 2.3.2 video interface video interface signals signal name i/o description dclko output dot clock signal for display dclki input dot clock input for external synchronization aoutr analog output analog signal (r) output aoutg analog output analog signal (g) output aoutb analog output analog signal (b) output hsync i/o*1 horizontal sync signal output horizontal sync input in external sync mode vsync i/o*1 vertical sync signal output vertical sync input in external sync mode csync output composite sync signal output eo i/o*1 even/odd field identification output 27 contains 8-bit precision d/a converters and outputs analog rgb signals uses csync signal and external circuits to generate composite video signal can output analog rgb signals synchronously to external video signal can synchronize to either dclki signal input or internal dot clock hsync and vsync reset to output mode. these signals must be pulled up externally. aoutr, aoutg and aoutb must be terminated at 75 ? . 1.1 v is input to vref. a bypass capacitor (with good high- frequency characteristics) must be inserted between vref and avs. acompr, acompg and acompb are tied to analog vdd via 0.1-f ceramic capacitors. vro must be pulled down to analog ground by a 2.7-k ? resistor. hsync, vsync and eo can tolerate input voltage levels of 5 v. however, never input 5 v to these pins when power is not supplied to MB86290A. (see the maximum voltage specification in the electrical characteristics.) when producing a non-interlaced display in the external synchronous mode, input 0 to the eo pin by using a pull-down resistor, etc. the gv signal switches graphics and video at chroma key operation. when video i is selected, the l level is output. 28 2.3.3 graphics memory interface graphics memory interface signals signal name i/o description md0-63 in/out graphics memory bus data ma0-13 output graphics memory bus address cke output clock enable mras output row address strobe mcas output column address strobe mwe output write enable mdqm0-7 output data mask mclko output graphics memory clock output mclki input graphics memory clock input this interface is used to transfer data from/to external memory. 64- mbit sdram can be used without glue logic. the data bus width is set to either 64 or 32 bits. in the 32-bit mode, md32-63 and mdqm4-7 must be kept open. mclki and mclko are tied to each other externally. 29 2.3.4 clock input clock input signals signal name i/o description clk input clock input signal s input pll reset signal ckm input clock mode signal inputs source clock for generating internal operation clock and display dot clock. normally, 4 fsc(= 14.31818 mhz) is input. an internal pll generates the internal operation clock of 100.22726 mhz and the display base clock of 200.45452 mhz. for the internal operation clock, use either the output clock of the internal pll (x7 of input clock) or the bus clock input (bclk1) from the host cpu. when the host cpu bus speed is 100 mhz, the bclk1 input should be selected. ckm clock mode l output from internal pll selected h host cpu bus clock (bclk1) selected at power-on, a low-level signal must be input to the s-signal pin for more than 500 ns and then set to high. after the s-signal input is set to high, a low-level signal must be input to xreset for another 300 s. 30 3 host interface 3.1 operation mode 3.1.1 host cpu mode select the host cpu by setting the mode signals as follows: cpu type setting mode1 mode0 cpu ll sh3 lh sh4 hl v832 hh reserved 3.1.2 endian MB86290A operates in little-endian mode. all the register address descriptions in these specifications are byte address in little endian. when using a big-endian cpu, note that the byte or word addresses are different from these descriptions. 31 3.2 access mode 3.2.1 sram interface data can be transferred to/from MB86290A using a typical sram access protocol. MB86290A internal registers, internal memory and external memory are all mapped to the physical address field of the host cpu. the host cpu can access any of them like a normal memory device. since MB86290A uses a hardware wait using the xrdy signal output, the respective hardware wait option of the host cpu must be enabled. cpu read the host cpu reads data from internal registers and memory of MB86290A in double-word (32 bit) units. cpu write the host cpu writes data to internal registers and memory of MB86290A in byte units. 3.2.2 fifo interface this interface transfers display lists in host memory. display list information is transferred efficiently by using a single address mode dma operation. this fifo is mapped to the physical address field of the host cpu so that the same data transfer can be performed in either the sram mode or dual address dma mode by specifying the fifo in the destination address. 32 3.3 dma transfer 3.3.1 data transfer unit dma transfer is performed in double-word (32 bit) units or 8 double-word (32 byte) units. byte and word access is not supported. note: 8 double-word transfer is supported only in the sh4 mode. 3.3.2 address mode dual address mode dma is performed at memory-to-memory transfer between host memory (source) and MB86290A internal registers, memory, or external memory (destination). both the host memory address and destination address is used. in the sh4 mode, the 1 double-word transfer (32 bits) and 8 double-word transfer (32 bytes) can be used. when the cpu transfer destination address is fixed, data can also be transferred to the fifo interface. however, in this case, even the sh4 mode supports only the 1 double-word transfer. note: the sh3 mode supports the direct address mode; it does not support the indirect address mode. single address mode (fifo interface) dma is performed between host memory (source) and fifo (destination). address output from the host cpu is only applied to designate the source, and the data output from the host memory is transferred to the fifo using the dack signal. in this mode, data read from the host memory and data write to the fifo occur in the same bus cycle. this mode does not support data write to the host memory. when the fifo is full, the dreq signal is tentatively negated and the dma transfer is suspended until the fifo has room for more data. the 1 double-word transfer (32 bits) and the 8 double-word transfer (32 bytes) can be used. note: the single-address mode is supported only in the sh4 mode. 33 3.3.3 bus mode MB86290A supports the dma transfer cycle steal mode and burst mode. either mode is selected by setting to the external dma mode. cycle steal mode ( in the v832 mode, the burst mode is called the single transfer mode. ) in the cycle steal mode, the bus right is transferred back to the host cpu at every dma transaction unit. the dma transaction unit is either 1 double- word (32 bits) or 8 double-words (32 b). burst mode ( in the v832 mode, the burst mode is called the demand transfer mode .) when dma transfer is started, the right to use the bus is acquired and the transfer begins. the data transfer unit can be selected from between the 1 double word (32 bits) and 8 double words (32 b). note: when performing dma transfer in the dual-address mode, a function for automatically negating dreq is provided based on the setting of the dbm register. 3.3.4 dma transfer request single-address mode dma is started when the MB86290A issues an external request to dmac of the host processor. set the transfer count in the transfer count register of the MB86290A and then issue dreq. fix the cpu destination address to the fifo address. dual-address mode dma is started by two procedures: the MB86290A issues an external request to dmac of the host processor, or the cpu itself is started (auto request mode, etc.). set the transfer count in the transfer count register of MB86290A and then issue dreq. note: the v832 mode requires no setting of the transfer count register. 34 3.3.5 ending dma transfer sh3/sh4 when the MB86290A transfer count register is set to 0, dma transfer ends and dreq is negated. v832 when the xtc signal from the cpu is low-asserted while the dmaak signal to MB86290A is high-asserted, the end of dma transfer is recognized and dreq is negated. the end of dma transfer is detected in two ways: the dma status register (dst) is polled, and an interrupt to end the drawing command (fd000000h) is added to the display list and the interrupt is detected. 35 3.4 interrupt request MB86290A issues interrupt requests to the host cpu. the following events issue interrupt requests. an interrupt request caused by each of these events is enabled/disabled independently by imr (interrupt mask register). external synchronization error vertical synchronization timing detect field synchronization timing detect command error command complete 36 3.5 transfer of local display list this is the mode in which the MB86290A internal bus is used to transfer the display list stored in the graphics memory to the fifo interface. during transfer of the local display list, the host bus can be used to perform read/write for the cpu. how to transfer list: store the display list in the local memory of the MB86290A, set the transfer source local address (lsa) and the transfer count (lco), and then issue a request (lreq). whether or not the local display list is currently being transferred is checked using the local transfer status register (lsta). fig. 3.1 transfer path for local display list cpu sdram host if sdram memory if fifo internal bus cpu bus 37 3.6 memory map the following table shows the memory map of MB86290A to the host cpu address field. the physical address is mapped differently in each cpu type (sh3, sh4 or v832). fig. 3.2 memory map table 3-1 address mapping in sh3/sh4 mode size resource base address (name) 32 mb to 256 kb graphics memory 00000000 64 kb host interface registers 01fc0000 (hostbase) 64 kb display engine registers 01fd0000 (displaybase) 64 kb internal texture memory 01fe0000 (texturebase) 64 kb drawing engine registers 01ff0000 (drawbase) 32 kb reserved * 02000000 the memory contents of 00000000-01ffffff are duplicated in this reserved field. table 3-2 address mapping in v832 mode size resource base address (name) 32 mb to 256kb graphics memory 00000000 64 kb host interface registers 00fc0000 (hostbase) 64 kb display engine registers 00fd0000 (displaybase) 64 kb internal texture memory 00fe0000 (texturebase) 64 kb drawing engine registers 00ff0000 (drawbase) register field graphics memory field reserved 32 mb-256 kb 256 kb 32 mb 0000000-1fbffff 1fc0000-1ffffff 2000000-3ffffff 64 mb field (sh3/sh4) register field 16 mb-256 kb 256 kb 0000000-0fbffff 0fcffff-0ffffff 16 mb field (v832) graphics memory field 38 4 graphics memory 4.1 configuration MB86290A uses local external memory (graphics memory) for drawing and display management. the configuration of this graphics memory is described as follows: 4.1.1 data type MB86290A handles the following types of data. display list can be stored in the host (main) memory as well. texture-tiling pattern and text pattern can be defined by a display list as well. drawing frame this is a rectangular image data field for 2d/3d drawing. two or more drawing frames can be used at once. the frame size can be bigger than the display frame size and display part of it. the drawing frame can be applied in 32-pixel units (both horizontally and vertically), and the maximum size is 4096 4096. both direct and indirect color modes can be used. display frame this is a rectangular image data field for display. up to four layers (three of graphics and one of video/graphics) can be overlaid and displayed at once. from bottom to the top, these are called the b (base), m (middle), w (window), and c (console) layers. z buffer the z buffer eliminates hidden surfaces in 3d drawing. the configuration is the same as drawing frame (defined for 3d drawing). 2 bytes/pixel of memory resources must be assigned. the z buffer must be cleared prior to 3d drawing. polygon draw flag buffer this is a work field for random shape drawing of multiple vertices. 1 bit/pixel should be defined for the drawing shape. this flag buffer must be cleared prior to drawing. 39 display list this is a set of commands and parameters executed by MB86290A. texture pattern this is pattern data for texture mapping. the 16-bit direct color mode must be used for texture pattern. the maximum size of this pattern is 256 256 pixels. the texture pattern is referenced from either graphics memory or internal texture buffer. cursor pattern this is the pattern data for hardware cursors. each pixel is described in 8-bit indirect color mode. two sets of 64 64-pixel patterns can be used. 4.1.2 memory layout each of these data items can be allocated anywhere in the graphics memory according to the respective register setting. 40 4.1.3 memory data format direct color color data is described in 15-bit rgb (rgb 5 bits, respectively). bit 15 is used as the alpha bit when producing a semi-transparent display for the c- layer. for other layers, set bit 15 to 0. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ar g b indirect color the color index code is in 8 bits. 76543210 color code z value this unsigned integer data describes the zvalue in a 3d coordinate. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 unsigned integer polygon draw flag this is binary data describing each pixel in 1 bit. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p15 p14 p13 p12 p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 p31 p30 p29 p28 p27 p26 p25 p24 p23 p22 p21 p20 p19 p18 p17 p16 41 texture/tiling pattern (direct color) this is color data described in the direct color mode (rgb 5 bits, respectively). the msb is an alpha bit used for the transparency effect of alpha blending. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ar g b tiling pattern (indirect color) this is a color index code in 8 bits. 76543210 color code cursor pattern this is a color index code in 8 bits. 76543210 color code 42 4.2 frame management 4.2.1 single buffer the entire or partial area of the drawing frame is assigned as a display frame. the display field is scrolled by relocating the position of the display frame. when the display frame crosses the border of the drawing frame, the other side of the drawing frame is displayed, assuming that the drawing frame is rolled over (top and left edges assumed logically connected to bottom and right edges, respectively). to avoid the affect of drawing on display, the drawing data can be transferred to the graphics memory in the blanking time period. 4.2.2 double buffer two drawing frames are set. while one frame is displayed, drawing is done at the other frame. flicker-less animation can be performed by flipping these two frames back and forth. flipping is done in the blanking time period. there are two flipping modes: automatically at every scan frame period, and by user control. the double buffer is assigned independently for the base and middle layers. when the screen partition mode is selected (so that both base and middle layers split into separate left and right windows), the double buffer can be assigned independently for left and right windows. 43 4.3 memory access 4.3.1 memory access by host cpu the graphics memory is mapped to the host cpu physical address field. the host cpu can access the graphics memory of MB86290A like a typical memory device. 4.3.2 priority of memory access the graphics memory accesses priority is as follows: 1. refresh 2. display 3. host cpu access 4. drawing 44 5 display controller 5.1 overview display control overlay of four display layers, screen partition, scroll, etc., is applicable. video timing generator the video display timing is generated according to the display resolution (from 320 240 to 1024 768). color look-up there are two sets of color look-up tables (pallet ram) for the indirect color mode (8 bits/pixel). cursor two sets of hardware cursor patterns (8 bits/pixel, 64 64 pixels each) can be used. external synchronization control graphics display can be synchronized with the external video display timing. 45 5.2 display function 5.2.1 layer configuration MB86290A supports four layers of display frames (c, w, m and b). furthermore, the m and b layers can be split into two separate windows at any position (l frame and r frame). all these six frames are assigned as logically separated fields in the graphics memory. configuration of display layers when the resolution exceeding the vga (640 x 480) is required, the layer count or pixel data which can be simultaneously displayed is restricted according to the capability of frame memory for supplying data. w-layer (window layer) 16 bits/pixel c-layer (console layer) top frame for console display 8, 16 bits/pixel m-layer (middle layer) additional overlay data 8,16 bits/pixel split into two partitions b-layer (base layer) navigation map data 8,16 bits/pixel split into two partitions 46 5.2.2 overlay simple priority mode the top layer has the higher priority. each pixel color is determined according to the following rules: 1. if the c layer is not transparent, the c-layer color is displayed. 2. if the c layer is transparent and w-layer image is at that position, the w-layer color is displayed. 3. if the c layer is transparent and there is no w layer image at that position, and if the m-layer color is not transparent, the m-layer color is displayed. 4. if the c and m layers are transparent and there is no w-layer image at that position, the b-layer color is displayed. transparent color is set by putting a specific transparent color code in the register. blend mode the w, m and b layers are managed in the same way as the simple priority mode described above. the result of the w/m/b layer priority color is blended with the c-layer color according to the blending ratio specified in the register. this mode is applied when the alpha bit of that pixel in the c layer is 1. if this alpha bit is set to 0, the result is the same as the simple priority mode. when the c-layer display priority is cursor display, the cursor color and c layer color are alpha blended at the pixel position with alpha bit = 1. the alpha blend ratio is calculated as follows: when brs bit of bratio register = 0 display color = ((c layer color x blend coefficient) + (mixed color of w/m/b layers x (1-blend coefficient)) when brs bit of bratio register = 1 display color = (c layer color x (1-blend coefficient)) + (mixed color of w/m/b layers x blend coefficient) 47 5.2.3 display parameters the display field is specified according to the following parameters. each parameter is set independently at the respective register. display parameters htp horizontal total pixels hsp horizontal synchronize pulse position hsw horizontal synchronize pulse width hdp horizontal display period hdb horizontal display boundary vtr vertical total raster vsp vertical synchronize pulse position vsw vertical synchronize pulse width vdp vertical display period wx window position x wy window position y ww window width wh window height when not splitting the screen, set hdp to hdb and display only the left side of the screen. the settings must meet the following size relationship: 0 < hdb hdp < hsp < hsp + hsw + 1 < htp 0 < vdp < vsp < vsp vsw + 1 < vtr hdp - hdb > 4 (in direct color mode), 8 (in indirect color mode) htp hsp hdb hdp wy wx ww wh vdp vsp vtr vsw hsw 48 5.2.4 display position control the graphic image data to be displayed is located in the logical 2d coordinate area (logical graphics field) in the graphics memory. there are six logical graphics fields as follows: c layer w layer ml layer (left field of m layer) mr layer (right field of m layer) bl layer (left field of b layer) br layer (right field of b layer) the correlation between the logical graphics field and physical display position is defined as follows: display position parameters oa origin address base address of logical graphics field. memory address of top left edge pixel in logical graphics field w stride width of logical graphics field. defined in 64-byte boundary h height height of logical graphics field. total raster (pixel) count of field da display address display base address. top left position address of display frame dx dy display position display base 2d coordinate stride (w) height (h) origin address (oa) display address (da) display position x,y (dx,dy) vdp logical frame display frame hdp 49 MB86290A scans the logical graphics field as if the entire field is rolled over in both the horizontal and vertical directions. by using this function, if the display frame crosses the border of the logical graphics field, the part outside the border is covered with the other side of the logical graphics field, which is assumed to be connected cyclically as shown below: wrap around management of display frame the relational expression of the x- and y-coordinates in the frame and their corresponding linear addresses (in bytes) is shown below. a(x,y) = x bpp/8 + 64wy (bpp = 8 or 16) the origin of the displayed coordinates must be within the frame. to be more specific, the parameters are subject to the following constraints: 0 dx < w ? 64 8/bpp (bpp = 8 or 16) 0 dy < h dx, dy, and da must indicate the same point within the frame. in other words, the following relationship must be established. da = oa + dx bpp/8 + 64w ? dy (bpp = 8 or 16) w l logical frame origin additionally drawn parts new display origin previous display origin 50 5.3 display color either direct color mode (16 bits/pixel) or indirect color mode (8 bits/pixel) can be used for the c, m, and b layers. only the direct color mode can be used for the w layer. 5.3.1 color look-up table MB86290A has two color look-up tables (pallets) for the indirect color mode. each pallet has 256 entries. a color data item contains 18 bits of data (rgb 6 bit, respectively), which is correlated to each color code specified in 8-bit data. therefore, each pallet can show 256 colors at one time out of 262,144 color selections. c-layer palette this pallet is dedicated to the c layer and hardware cursors. if the overlay blend mode is used, an alpha bit must be set at each color data. when this alpha bit is set to 1, color blending between the c-layer pixel and w/m/b layer pixels is performed according to the priority order specified in the overlay section. this blending option cannot be used for the hardware cursor. m/b-layer palette this pallet is shared by the m and b layers. if both the m and b layers are set to the indirect color mode, they share this same color pallet. 5.3.2 chroma-key operation MB86290A performs superimpose using the chroma-key function. when the key color of this chroma-key operation matches the color of the c layer during the display scan period, the gv signal output becomes l level. the graphics signal output from MB86290A and the external video signal can be switched by using this signal. 51 5.4 cursor 5.4.1 cursor display function MB86290A can display two hardware cursors simultaneously. each cursor is specified as 64 x 64 pixels, and the style pattern is set in the graphics memory. only the indirect color mode (8 bits/pixel) can be used and the c- layer pallet is used for the color look-up. however, transparent color management (transparent color code setting and management of code 0) is different from ordinary c-layer pixels 3 alpha blending cannot be used for the cursor color and the alpha bit in the color data registered to the color palette is ignored. 5.4.2 cursor management the display priority for hardware cursors is programmable. the cursor can be displayed either on top or underneath the c layer using this feature. a separate setting can be made for each hardware cursor. if part of a hardware cursor crosses the display frame border, the part outside the border is not shown. however, with cursor 1 displayed over the c-layer and cursor 0 displayed under the c-layer, the cursor 1 display has priority over the cursor 0 display. 52 5.5 processing flow for display data processing such as layer overlapping (superimposing) and chroma key is performed as follows: fig. 5.1 display data processing flow ml-layer transparent color specifies transparent color code for left side of m layer the color code corresponding to the transparent color is used to output transparent image data for the lower layer. ml-layer transparent color specifies transparent color code for right side of m layer the color code corresponding to the transparent color is used to output transparent image data for the lower layer. mr-layer trans- parent color color ml-layer trans- parent color color b-layer m-layer w-layer pallet for m&b cursor1 c-layer select cursor0 blend overlap by priority select select bit pixel bit pixel select dac compare c-layer blend enable chroma key mode key color gv output analog rgb output blend mode overlap by priority overlap by priority c-layer trans- p arent color cursor over- lap mode color cursor trans- parent color color blend ratio pallet for c 53 c-layer transparent color specifies transparent color code for c layer the color code corresponding to the transparent color is used to output transparent image data for the lower layer. cursor transparent color specifies transparent color code for cursor cursor priority mode specifies whether or not to display cursor above c layer blend mode defines correspondence between blend coefficients and variables used when applying blend coefficients blend ratio specifies blend ratio with accuracy of 1/16 blend enable specifies whether or not to use blend chroma key mode selects display data used to compare chroma keys the data for the c-layer or final tier can be selected. key color sets color code compared with display data when display data matches the color code, 0 is output to the gv pin. 54 5.6 synchronization control 5.6.1 applicable display resolution the following table shows typical display resolutions and their sync signal frequencies. the pixel clock frequency is determined by setting the division rate of the display reference clock. the display reference clock is either the internal pll (200.45452 mhz at input frequency of 14.31818 mhz), or the clock supplied to the dclki input pin. the following table gives the clock division rate used when the internal pll is the display reference clock: resolution division rate of reference clock pixel frequency horizontal total pixel count horizontal frequency vertical total raster count vertical frequency 320 240 1/30 6.7 mhz 424 15.76 khz 263 59.9 hz 400 240 1/24 8.4 mhz 530 15.76 khz 263 59.9 hz 480 240 1/20 10.0 mhz 636 15.76 khz 263 59.9 hz 640 480 1/8 25.1 mhz 800 31.5 khz 525 59.7 hz 854 480 1/6 33.4 mhz 1062 31.3 khz 525 59.9 hz 800 600 1/5 40.1 mhz 1056 38.0 khz 633 60.0 hz 1024 768 1/3 66.8 mhz 1389 48.1 khz 806 59.9 hz pixel frequency = 14.31818 mhz 14 x reference clock division rate (when internal pll selected) = dclki input frequency reference clock division rate (when dclki selected) horizontal frequency = pixel frequency/horizontal total pixel count vertical frequency = horizontal frequency/vertical total raster count 5.6.2 interlace display the MB86290A can generate both a non-interlace display and an interlace display. for the interlace display, the 1st, 3rd, (2n+1)th rasters of the display screen are output to odd fields, and 2nd, 4th, 2n-th rasters of the display screen are output to even fields. 55 5.6.3 external synchronization display scan can also be synchronized to external hsync/vsync signals. when the external synchronization mode is set at the register, MB86290A starts sampling the hsync signal input and displays the graphics output synchronized to the external video signals. either the internal display base clock or dclki input can be used for this sampling clock. also, by using the chroma-key function, superimpose is performed with external circuitry as follows: fig. 5.2 example of external synchronization circuit the external synchronous mode is set using the esy bit of the dcm register. when the external synchronous mode is set, the hsync, vsync, and eo pins of the MB86290A are placed in the input mode. after this, supply external sync signals by using the tristate buffer. also, when exiting from the external synchronous mode, cut the external synchronous input and then set the internal esy bit of the MB86290A to off. with the MB86290A sync signal output set to on, avoid setting the buffer for external sync signals to on. use the above procedure to control so that the concurrent-on duration will not occur. MB86290A video sw analog rgb out analog rgb in superimposed analog rgb out hsync in vsync in gv eo in (pedestal clump input) compare 3 states keyc external sync enable hsync out vsync out eo out c w m b cursor 0 cursor 1 c dac buffer register ckm bit esy bit display timming generator overlap hsync vsync eo 56 horizontal synchronization is controlled by the following state transitions: state transitions are controlled mainly using the count values of the horizontal pixel counter. the display duration is equivalent to the disp state. when the value of the horizontal pixel counter reaches the setting of the hdp register, the display duration ends, causing a transition from the disp state to the fporch state (front porch). with the fporch state established, when the value of the horizontal pixel counter reaches the setting of the hsp register, a transition is made to the sync state. in the sync state, external horizontal synchronization signals are supplied. the MB86290A detects the negation edge of the external horizontal synchronization pulse to perform synchronization. when the external horizontal synchronization signal is detected, a transition is made to the bporch state (back porch). in the sync state, the horizontal pixel counter stops, but the horizontal synchronization pulse counter starts incrementing from 0. when the value of the counter reaches the setting of the hsw register, a transition is made to the bporch state without detecting the external horizontal synchronization signal. with the bporch state established, when the value of the horizontal pixel counter reaches the setting of the htp register, the horizontal pixel counter is reset and a transition is made to the disp state, starting display of the next raster. horizontal pixel counter reaches htp disp sync horizontal pixel counter reaches hdp otherwis otherwis otherwis when horizontal pixel counter reaches htp, counter initialized external horizontal synchronization detected, or horizontal synchronization pulse counter reaches hsw otherwis horizontal pixel counter suspended and horizontal synchronization pulse counter starts counting horizontal pixel counter reaches hsp fporch bporch 57 the vertical synchronization is controlled by the following state transitions: state transitions are mainly controlled using the count values of the raster counter. the display duration is equivalent to the disp state. when the value of the raster counter reaches the setting of the vdp register, the display duration ends, causing a transition from the disp state to the fporch state (front porch). in the fporch state, the processing waits for the external vertical synchronization pulse to be asserted. when assertion of the external vertical synchronization pulse is detected, a transition is made to the sync state. in the sync state, the processing waits for the external vertical synchronization signal to be negated. when the negation is detected, a transition is made to the bporch state (back porch). with the bporch state established, when the value of the raster counter reaches the setting of the vtr register, the raster counter is reset and a transition is made to the disp state, starting display of the next field. raster counter reaches vtr disp raster counter reaches vdp otherwis otherwis otherwis counter initialized when raster counter reaches vtp negation of external vertical synchronization pulse detected otherwis assertion of external vertical synchronization pulse detected fporch bporch sync 58 5.7 video interface 5.7.1 ntsc output if an ntsc signal is required, an ntsc encoder device should be connected externally as shown below: fig. 5.3 example of ntsc encoder connection csync aoutr csync-in r-in g-in b-in MB86290A mb3516a video-out aoutg aoutb 59 6 drawing control 6.1 coordinates 6.1.1 drawing coordinate MB86290A manages a drawing frame as a 2d coordinate with the origin at the top left edge. the maximum coordinate is 4096 x 4096. each drawing frame is located in the graphics memory by setting the address of the origin and width (pixel size of x span). although the maximum size of y span does not need to be specified, take care about the memory size allocation so as not to overlap any other frames. also, setting the clip field (top left and bottom right coordinates in registers) prevents drawing of all images outside the border of the clip window. x (max. 4096 ?j y (max. 4096) base point draw frame size x draw frame size y (xmin, ymin) (xmax, ymax) clip border 60 6.1.2 texture coordinate this is another 2d coordinate specified as s and t (s: horizontal, t: vertical). any integer in a range of ? 512 to +511 can be used as the s and t coordinates. the texture coordinate is correlated to the 2d coordinate of a vertex. all vertices forming a polygon have correlated texture coordinates. one texture style pattern can be applied to up to 256 256 pixels. the applied texture size is set in the register. when the s and t coordinate exceeds the maximum size of the texture style pattern, the repeat, cramp or border color option is selected. s(max.+512/-512) t(max.+512/-512) base point max.256pixel max.256pixel texture pattern 61 6.1.3 frame buffer for drawing, the following area must be assigned to the graphics memory. the frame size (number of pixels on x span) is common for these areas. drawing frame the results of drawing are contained in the graphical image data area. both the direct and indirect color mode are applicable. z buffer nts area dr used to eliminate hidden surfaces in drawinga3d graphics. 2i bytes/pixel of area is required. polygon draw flag buffer this area is used to perform polygon drawing hidden surfaces in 3d graphics drawing. 1bit/pixel of area is required. 1 line is aligned by byte to byte. 62 6.2 polygon drawing 6.2.1 drawing primitives MB86290A supports the following primitive types: - point - line - triangle - fast2dline - fast2dtriangle - polygon 6.2.2 polygon drawing an irregular polygon (including concave shape) is drawn by dedicated hardware as follows: 1. execute polygonbegin command initialize polygon draw enginew 2. draw vertices. draw outline of polygon and plot all vertices to polygon draw flag buffer utilizing fast2dtriangle primitive. 3. execute polygonend command. copy shape in polygon draw flag buffer to drawing frame and fill shape with color or specified tiling pattern. 63 6.2.3 drawing parameters MB86290A differentiates triangles (right triangle and left triangle) according to the locations of three vertices as follows (not used for fast2dtriangle): the following parameters are required for drawing triangles (for fast2dtriangle, x and y coordinates of each vertex are specified). note: be careful about the positional relationship between coordinates xs, xus, and xls. for example, in the above diagram, when a right-hand triangle is drawn using the parameter that shows the coordinates positional relationship xs (upper edge start y coordinate) > xus or xs (lower edge start y coordinate) > xls, the expected picture may not be drawn. v0 upper side long side v1 lower side v2 upper triangle lower triangle v1 v0 v2 upper side lower side long side upper triangle lower triangle right triangle left triangle xus xls ys xs,zs,rs,gs,bs,ss,ts,qs upper side start y coordinate dxdy dzdy drdy dgdy dbdy dsdy dtdy dqdy dxudy dxldy lower side start y coordinate dzdx,drdx,dgdx,dbdx, dsdx,dtdx,dqdx usn lsn 64 ys y-coordinate start position of long side xs x-coordinate start position of long side xus x-coordinate start position of upper side xls x-coordinate start position of lower side zs z-coordinate start position of long side rs r value at (xs, ys, zs) of long side gs g value at (xs, ys, zs) of long side bs b value at (xs, ys, zs) of long side ss s-coordinate of texture at (xs, ys, zs) of long side ts t-coordinate of texture at (xs, ys, zs) of long side qs q (perspective correction value) of texture at (xs, ys, zs) of long side dxdy x dda value of long side dxudy x dda value of upper side dxldy x dda value of lower side dzdy z dda value of long side drdy r dda value of long side dgdy g dda value of long side dbdy b dda value of long side dsdy s dda value of long side dtdy t dda value of long side dqdy q dda value of long side usn number of spans (rasters) of top triangle lsn number of spans (rasters) of bottom triangle dzdx z dda value of horizontal way drdx r dda value of horizontal way dgdx g dda value of horizontal way dbdx b dda value of horizontal way dsdx s dda value of horizontal way dtdx t dda value of horizontal way dqdx q dda value of horizontal way 6.2.4 anti-aliasing function MB86290A performs anti-aliasing to eliminate jaggies on line edges and make lines appear smooth. to use this function at the edges of primitives, redraw the primitive edges with anti-alias lines. 65 6.3 bit map operation 6.3.1 blt a rectangular shape in pixel units can be transferred between two separate physical memory areas as follows: (1) from host cpu to drawing frame memory (2) from graphics memory (other than drawing frame memory area) to drawing memory (3) from host cpu to internal texture memory (4) from graphics memory to internal texture memory when drawing frame memory is designated as the destination, the result of logical calculation between the source and current value in the designated destination can be stored as well. if part of the source and destination of the blt field are physically overlapped in the display frame, the start address (from which vertex the blt field to be transferred) must be set carefully. usage caution : when transferring a rectangle from one graphics memory to another graphics memory (drawing frames included), or from the host cpu to the internal texture memory, the width of the rectangle must be at least 5 pixels (in direct color mode) or 9 pixels (in indirect color mode). 6.3.2 pattern data format MB86290A can handle three bit map data formats: indirect color mode (8 bits/pixel), direct color mode (16 bits/pixel), and binary bit map (1 bit/pixel). the direct color mode is used for texture patterns. either the indirect or direct color mode is used for tiling patterns. the binary bit map is used for character/font patterns, where foreground color is used for bitmap = 1 pixel, and background color is applied for bitmap = 0 pixels. 66 6.4 texture mapping texture mapping is supported when the direct color mode (16 bits/pixel) drawing frame is used. 6.4.1 texture size MB86290A reads texcel data from the specified texture coordinate (s, t) position, and pastes that data at the correlated pixel position of the polygon. the applicable texture data size is 16, 32, 64, 128 or 256 pixels per s and t, respectively. texture mapping is used only when the direct color mode (16bit/pixel) is used. 6.4.2 texture memory texture pattern data is stored in either the MB86290A internal texture buffer or external graphics memory. the internal texture buffer size is 8 kbyte and can hold up to 64 64 pixels of texture. if the texture pattern size is smaller than 64 64pixels, it is best to store it in the internal texture buffer because the texture mapping speed is faster. 67 6.4.3 texture lapping if a negative or larger than applicable value is specified as the texture coordinate (s, t), according to the setting, one of these options (repeat, cramp or border) is selected for the out-of-range texture mapping. the mapping image for each case is shown below: repeat this just masks the upper bits of the applied (s, t) coordinate and enables the lower bits of the coordinate within the specified texture pattern size. when the texture pattern size is 64 64pixels, it masks the upper bits of the integer part of (s, t) the coordinate and enables the lower 6 bits. cramp when the applied (s, t) coordinate is either negative or larger than the specified texture pattern size, cramp the (s, t) coordinate as follows: s < 0 s = 0 s > texture x size C 1 s = texture x size C 1 border when the applied (s, t) coordinate is either negative or larger than the specified texture pattern size, the outside of the specified texture pattern is rendered in the border color. repeat cramp border 68 6.4.4 filtering MB86290A supports two texture filtering modes: point filtering, and bi-linear filtering. point filtering this mode uses the texcel data specified by the (s, t) coordinate. the nearest texcel in the texture pattern is chosen according to the calculated (s, t) coordinate. bi-linear filtering this mode picks the four nearest texcels from the calculated (s, t) coordinate. the color is blended and the texcel image is defined according to the distance between each of these texcels and the calculated (s, t) coordinate. note: this mode can be used when the internal memory is specified as the texture memory mode. 0. 0. 1. 1. 2. 0. 1. 1. 2. 0. 0. 1. 1. 2. 0. 1. 1. 2. c 0 c 1 c 0 c 1 69 6.4.5 perspective correction this function adjusts the depth distortion of the 3d projection in the texture mapping process. for this adjustment, the q element of the texture coordinate (q = 1/w) is defined from the 3d coordinate of the correlated vertex. this q value is used after normalizing in the range between 0.0 and 1.0. 6.4.6 texture blending MB86290A supports the following three texture blending modes: decal this mode displays the mapped texcel color regardless the native polygon color. modulate this mode multiplies the native polygon color (c p ) and sampled texcel color (c r ) and display the result (c o ). c 0 = c r x c p stencil this mode uses the msb to select the display color from the sampled texcel color. msb = 1: texcel color msb = 0: polygon color 70 6.5 rendering 6.5.1 tiling tiling reads the pixel color from the correlated tiling pattern and maps it onto the polygon. the tiling pixel is determined by the coordinate of the correlated pixel irrespective of the primitive position and size. since the tiling pattern is stored in the internal texture buffer, this function and texture mapping cannot be used at the same time. also, the tiling pattern size is limited to within 64 x 64 pixels. fig. 6.4 example of tiling operation 71 6.5.2 alpha blending alpha blending blends the pixels native color and current color of that pixel position according to the blending ratio parameter set in the alpha register. this function cannot be used simultaneously with logical calculation. it can be used only when the direct color mode (16 bits/pixel) is used. the blended color c is calculated as shown below when the native color of the pixel to be rendered is c p , the current pixel color of that position is c f , and the alpha value set in the alpha register is a: c = c p a + (1-a) c f the alpha value is specified as 8-bit data. 00h means alpha value 0% and ffh means alpha value 100%. when the texture mapping function is enabled, the following blending modes are applicable: normal blends post texture mapping color with current frame buffer color stencil uses msb of texcel color to select display color: msb = 1: texcel color msb = 0: current frame buffer color stencil alpha uses msb of texcel color to select and activate alpha-blend function: msb = 1: alpha blend texcel color and current frame buffer color msb = 0: current frame buffer color 6.5.3 logical calculation this mode executes a logical calculation between the new pixel color to be rendered and the current frame memory color and displays the result. alpha blending cannot be used when this function is used. type id operation type id operation clear 0000 0 and 0001 s & d copy 0011 s or 0111 s | d nop 0101 d nand 1110 !(s & d) set 1111 1 nor 1000 !(s | d) copy inverted 1100 !s xor 0110 s xor d invert 1010 !d equiv 1001 !(s xor d) and reverse 0010 s & !d and inverted 0100 !s & d or reverse 1011 s | !d or inverted 1101 !s | d 72 6.5.4 hidden surface management this function compares the z value of a new pixel to be rendered and the existing z value in the z buffer. display/not display is switched according to the z-compare mode setting. define the z-buffer access options in the zwritemask mode. the z-comparison type is determined by the z compare mode. 1 compare z values, no z buffer overwrite zwritemask 0 compare z values and overwrite result to z buffer z compare mode id condition never 000 never draw always 001 always draw less 010 draw if pixel z value < current z buffer value lequal 011 draw if pixel z value < current z buffer value equal 100 draw if pixel z value = current z buffer value gequal 101 draw if pixel z value < current z buffer value greater 110 draw if pixel z value > current z buffer value notequal 111 draw if pixel z value < current z buffer value 73 6.6 drawing attributes 6.6.1 line draw attributes when line draw operations are performed, the following attributes apply: line draw attributes attribute description line width line width selectable in range of 1-32 pixels broken line draw specify broken line pattern in 32-bit data anti-alias line edge smoothed when anti-aliasing enabled 6.6.2 triangle draw attributes when triangle draw operations are performed, the following attributes apply. texture mapping and tiling have separated texture attributes: triangle draw attributes attribute description shading gouraud shading or flat shading selectable alpha blending set alpha blend enable per polygon blending parameter set color blend ratio of alpha blend 74 6.6.3 texture attributes the following attributes apply for texture mapping: texture attributes attribute description texture mode select either texture mapping or tiling texture memory mode select either internal texture buffer or external graphics memory to use in texture mapping texture filter select either point sampling or bi-linear filtering the bilinear filter can be specified when the internal memory is specified as the texture memory mode. texture coordinate correction select either linear or perspective correction texture wrap select either repeat or cramp of texture pattern texture blend mode select either decal or modulate 6.6.4 character/font drawing and blt attributes when character/font pattern draw and blt draw are performed, the following attributes apply: character/font pattern and blt attributes attribute description character pattern enlarge/shrink 2 2, 2 horizontal, 1/2 1/2, 1/2 horizontal character pattern color set character color and background color logical calculation mode specify two source logical calculation mode in blt operation 75 6.7 display list 6.7.1 overview display list is a set of display list commands, parameters and pattern data. all display list commands in a display list are executed consequently (note that display list command does not mean draw command). the display list is transferred to the display list fifo by one of the following methods: cpu write to display fifo dma transfer from main memory to display fifo register set to transfer from graphics memory to display fifo display list command-1 data 1-1 data 1-2 data 1-3 display list command-2 data 2-1 data 2-2 data 2-3 ------ display list 76 6.7.2 header format format overview format 31 24 23 16 15 0 format 1 type reserved reserved format 2 type count address format 3 type reserved reserved vertex format 4 type reserved reserved flag vertex format 5 type draw command reserved format 6 type draw command count format 7 type draw command reserved vertex format 8 type draw command reserved flag vertex format 9 type reserved reserved flag description of each field type display list type drawcommand draw command count number of parameters excluding header address address value used at data transfer vertex vertex number flag dedicated attribute flag of display list command vertex number specified in vertex code vertex vertex number (line) vertex number (triangle) 00 v0 v0 01 v1 v1 10 inhibited v2 11 inhibited inhibited 77 6.7.3 display list command overview the following table lists the MB86290A display list commands. type draw command description nop - no operation interrupt - interrupt request to host cpu sync - synchronization of events setregister - data set to register normal data set to fast2dtriangle vrtx register setvertex2i polygonbegin initialization of border rectangle calculation of multiple vertices random shape polygonend polygon flag clear (post random shape drawing operation) flush_fb/z flushes drawing pipelines draw all draw commands issue draw command drawpixel pixel plot point drawpixelz pixelz plot point with z value xvector draw line (*1) yvector draw line (*2) antixvector draw line with anti-alias option (*1) drawline antiyvector draw line with anti-alias option (*2) drawline2i zerovector draw fast2dline (start from vertex 0) drawline2ip onevector draw fast2dline (start from vertex1) trapright draw right triangle drawtrap trapleft draw left triangle drawvertex2i trianglefan draw fast2dtriangle drawvertex2ip flagtrianglefan draw fast2dtriangle for multiple vertices random shape drawrect bltfill fill rectangle with one color or tiling pattern drawrectp clearpolyflag clear polygon flag buffer drawbitmap bltdraw draw rectangle pattern drawbitmapp bitmap draw binary bit map pattern (character) bltcopy topleft bitblt transfer from left upper vertex bltcopyp topright bitblt transfer from right upper vertex bltcopy alternate bottomleft bitblt transfer from left lower vertex bltcopy alternatep bottomright bitblt transfer from right lower vertex loadtexture load texture pattern loadtexture loadtile load tile pattern loadtexture load texture pattern from graphics memory blttexture loadtile load tile pattern from graphics memory note (*1) -pai/4 ? line angle ? pai/4 (*2) -pai/2 ? line angle ? -pai/4, or pai/4 ? line angle ? pai/2 78 type field code table type code drawpixel 0000_0000 drawpixelz 0000_0001 drawline 0000_0010 drawline2i 0000_0011 drawline2ip 0000_0100 drawtrap 0000_0101 drawvertex2i 0000_0110 drawvertex2ip 0000_0111 drawrectp 0000_1001 drawbitmapp 0000_1011 bitcopyp 0000_1101 bitcopyalternatep 0000_1111 loadtexturep 0001_0001 blttexturep 0001_0011 setvertex2i 0111_0000 setvertex2ip 0111_0001 draw 1111_0000 setregister 1111_0001 sync 1111_1100 interrupt 1111_1101 nop 1111_1111 79 draw command code table (1) drawcommand code pixel 000_00000 pixelz 000_00001 xvector 001_00000 yvector 001_00001 xvectornoend 001_00010 yvectornoend 001_00011 xvectorblpclear 001_00100 yvectorblpclear 001_00101 xvectornoendblpclear 001_00110 yvectornoendblpclear 001_00111 antixvector 001_01000 antiyvector 001_01001 antixvectornoend 001_01010 antiyvectornoend 001_01011 antixvectorblpclear 001_01100 antiyvectorblpclear 001_01101 antixvectornoendblpclear 001_01110 antiyvectornoendblpclear 001_01111 zerovector 001_10000 onevector 001_10001 zerovectornoend 001_10010 onevectornoend 001_10011 zerovectorblpclear 001_10100 onevectorblpclear 001_10101 zerovectornoendblpclear 001_10110 onevectornoendblpclear 001_10111 antizerovector 001_11000 antionevector 001_11001 antizerovectornoend 001_11010 antionevectornoend 001_11011 antizerovectorblpclear 001_11100 antionevectorblpclear 001_11101 antizerovectornoendblpclear 001_ 11110 antionevectornoendblpclear 001_ 11111 80 draw command code table (2) drawcommand code bltfill 010_00001 bltdraw 010_00010 bitmap 010_00011 topleft 010_00100 topright 010_00101 bottomleft 010_00110 bottomright 010_00111 loadtexture 010_01000 loadtile 010_01001 trapright 011_00000 trapleft 011_00001 trianglefan 011_00010 flagtrianglefan 011_00011 flush_fb 110_00001 flush_z 110_00010 polygonbegin 111_00000 polygonend 111_00001 clearpolyflag 111_00010 normal 111_11111 81 6.7.4 details of display list commands all parameters belonging to their command are set in correlated registers. the definition of each parameter is figured out in the section of each command description. nop (format1) 31 24 23 16 15 0 nop reserved reserved no operation interrupt (format1) 31 24 23 16 15 0 interrupt reserved reserved generates interrupt request to host cpu sync (format9) 31 24 23 16 15 4 0 sleep reserved reserved flag suspends all subsequent display list operations until event specified in flag field detected flag: bit # 4 3 2 1 0 bit field name reserved reserved reserved reserved vblank bit0 vblank vblank synchronization 0 no operation 1 wait for vsync detection 82 setregister (format2) 31 24 23 16 15 0 setregister count address (val 0) (val 1) - - - (val n) sets data at consecutive registers count: data word count (in double-word unit) address: register address set the register address as the byte address/4 (address in double- word units). setvertex2i (format8) 31 24 23 16 15 4 3 2 1 0 setvertex2i draw command reserved flag vertex xdc ydc sets vertices data for fast2dline or fast2dtriangle command at registers commands: normal set vertex data (x, y). polygonbegin start calculation of circumscribed rectangle for random shape to be drawn. calculate vertices of rectangle including all vertices of random shape defined between polygonbegin and polygonend. flag: not used setvertex2ip (format8) 31 24 23 16 15 4 3 2 1 0 setvertex2i draw command reserved flag vertex ydc xdc sets vertices data for fast2dline or fast2dtriangle command to registers 83 only the packed integer format can be used specify these vertices. command: normal set vertices data. polygonbegin start calculation of circumscribed rectangle of random shape to be drawn. calculate vertices of rectangle including all vertices of random shape defined between polygonbegin and polygonend. flag: not used draw (format5) 31 24 23 16 15 0 draw draw command reserved executes draw command all parameters required at execution of a draw command must be set at their appropriate registers. commands: polygonend draw random shape of multiple vertices. fill random shape with color according to flags generated by flagtrianglefan command and information of circumscribed rectangle generated by polygonbegin command. flush_fb this command flushes drawing data in the drawing pipeline into the graphics memory. place this command at the end of the display list. flush_z this command flushes z-value data in the drawing pipeline into the graphics memory. when using the z buffer, place this command together with the flush_fb command at the end of the display list. drawpixel (format5) 31 24 23 16 15 0 deawpixel draw command reserved pxs pys plots pixel command: pixel plot pixel (without z value). 84 drawpixelz (format5) 31 24 23 16 15 0 deawpixel draw command reserved pxs pys pzs plots 3d pixel command: pixelz plot pixel (with z value). 85 drawline (format5) 31 24 23 16 15 0 drawline draw command reserved lpn lxs lxde lys lyde draws line start drawing after setting all parameters at line draw registers. commands: xvector draw line (*1). yvector draw line (*2). xvectornoend draw line without end point (*1). yvectornoend draw line without end point (*2). xvectorblpclear draw line (*1). prior to drawing, clear reference position of broken line pattern. yvectorblpclear draw a line (*2) prior to drawing, clear reference position of broken line pattern. xvectornoendblpclear draw line without end point (*1). prior to drawing, clear reference position of broken line pattern. yvectornoendblpclear draw line without end point (*2). prior to drawing, clear reference position of broken line pattern. antixvector draw anti-alias line (*1). antiyvector draw anti-alias line (*2). antixvectornoend draw anti-alias line without end point (*1). antiyvectornoend draw anti-alias line without end point (*2). antixvectorblpclear draw anti-alias line (*1). prior to drawing, clear reference position of broken line pattern. antiyvectorblpclear draw anti-alias line (*2). prior to drawing, clear reference position of broken line pattern. antixvectornoendblpclear draw anti-alias line without end point (*1). prior to drawing, clear reference position of broken line pattern. antiyvectornoendblpclear draw anti-alias line without end point (*2). prior to drawing, clear reference position of broken line pattern note (*1) -pai/4 ? line angle ? pai/4 (*2) -pai/2 ? line angle ? -pai/4, orpai/4 ? line angle ? pai/2 86 drawline2i (format7) 31 24 23 16 15 0 drawline2i draw command reserved vertex lfxs 0 lfys 0 draws fast2dline start drawing after setting parameters at the fast2dline draw registers. integer data can only be used for vertices. commands: zerovector draw line from vertex 0 to vertex 1. onevector draw line from vertex 1 to vertex 0. zerovectornoend draw line without end point from vertex 0 to vertex 1. onevectornoend draw line without end point from vertex 1 to vertex 0. zerovectorblpclear draw line from vertex 0 to vertex 1. prior drawing, clear reference position of broken line pattern. onevectorblpclear draw line from vertex 1 to vertex 0. prior to drawing, clear reference position of broken line pattern. zerovectornoendblpclear draw line from vertex 0 to vertex 1 without end point. prior to draw, clear reference position of broken line pattern. onevectornoendblpclear draw line from vertex 1 to vertex 0 without end point. prior to drawing, clear reference position of broken line pattern. antizerovector draw anti-alias line from vertex 0 to vertex 1. antionevector draw anti-alias line from vertex 1 to vertex 0. antizerovectornoend draw anti-alias line without end point from vertex 0 to vertex 1. antionevectornoend draw anti-alias line without end point from vertex 1 to vertex 0. antizerovectorblpclear draw anti-alias line from vertex 0 to vertex 1. prior to drawing, clear reference position of broken line pattern. antionevectorblpclear draw anti-alias line from vertex 1 to vertex 0. prior to drawing, clear reference position of broken line pattern. antizerovectornoendblpclear draw anti-alias line from vertex 0 to vertex 1 without end point. prior to drawing, clear reference position of broken line pattern. antionevectornoendblpclear draw anti-alias line from vertex 1 to vertex 0 without end point. prior to drawing, clear reference position of broken line pattern. 87 drawline2ip (format7) 31 24 23 16 15 0 drawline2ip draw command reserved vertex lfys lfxs draws fast2dline start drawing after setting parameters at fast2dline draw registers. only packed integer data can be used for vertices. commands: zerovector draw line from vertex 0 to vertex 1. onevector draw line from vertex 1 to vertex 0. zerovectornoend draw line without end point from vertex 0 to vertex 1 onevectornoend draw line without end point from vertex 1 to vertex 0 zerovectorblpclear draw line from vertex 0 to vertex 1. prior to drawing, clear the reference position of the broken line pattern. onevectorblpclear draw line from vertex 1 to vertex 0. prior to drawing, clear reference position of broken line pattern. zerovectornoendblpclear draw line from vertex 0 to vertex 1 without end point. prior to drawing, clear reference position of broken line pattern. onevectornoendblpclear draw line from vertex 1 to vertex 0 without end point. prior to drawing, clear reference position of te broken line pattern. antizerovector draw anti-alias line from vertex 0 to vertex 1. antionevector draw anti-alias line from vertex 1 to vertex 0. antizerovectornoend draw anti-alias line without end point from vertex 0 to vertex 1. antionevectornoend draw anti-alias line without end point from vertex 1 to vertex 0. antizerovectorblpclear draw anti-alias line from vertex 0 to vertex 1. prior to drawing, clear reference position of broken line pattern. antionevectorblpclear draw anti-alias line from vertex 1 to vertex 0. prior to drawing, clear reference position of broken line pattern. antizerovectornoendblpclear draw anti-alias line from vertex 0 to vertex 1 without end point. prior to drawing, clear reference position of broken line pattern. antionevectornoendblpclear draw anti-alias line from vertex 1 to vertex 0 without end point. prior to drawing, clear reference position of broken line pattern. 88 drawtrap (format5) 31 24 23 16 15 0 drawtrap draw command reserved ys 0 xs dxdy xus dxudy xls dxldy usn 0 lsn 0 draws triangle operation is started after setting all the related parameters at the plane draw registers. commands: trapright draw right triangle. trapleft draw left triangle. drawvertex2i (format7) 31 24 23 16 15 0 drawvertex2i draw command reserved vertex xdc 0 ydc 0 draws fast2dtriangle operation is started after setting all the related parameters at the plane draw registers. commands: trianglefan draw fast2dtriangle. flagtrianglefan draw fast2dtriangle for random shape with multiple vertices. drawvertex2ip (format7) 31 24 23 16 15 0 drawvertex2ip draw command reserved vertex ydc xdc draws fast2dtriangle 89 operation is started after setting all the related parameters at plane draw registers only the packed integer format can be used for vertex coordinates. commands: trianglefan draw fast2dtriangle. flagtrianglefan draw fast2dtriangle for random shape with multiple vertices. 90 drawrectp (format5) 31 24 23 16 15 0 drawrectp draw command reserved rys rxs rsizey rsizex fills rectangle the designated rectangle is filled with the current color after setting all the related parameters at the rectangle registers. commands: bltfill fill rectangle with current color (single) or current tiling pattern. clearpolyflag fill polygon flag field with 0. the size is defined in rsizex,y. drawbitmapp (format6) 31 24 23 16 15 0 drawbitmapp draw command count rys rxs rsizey rsizex (pattern 0) (pattern 1) - - - (pattern n) draws rectangle commands: bltdraw draw rectangle of 8 bits/pixel or 16 bits/pixel. drawbitmap draw binary bitmap character pattern. bit0 is drawn in transparent or background color, and bit1 is drawn in foreground color. background color is specified in the bc register, and foreground color is specified in the fc register. 91 bltcopyp (format5) 31 24 23 16 15 0 bltcopyp draw command reserved srys srxs drys drxs brsizey brsizex copies rectangle pattern within one drawing frame for brsizex, specify at least 5 pixels (when direct color mode used) or 9 pixels (when indirect color mode used). commands: topleft start bitblt transfer from top left vertex. topright start bitblt transfer from top right vertex. bottomleft start bitblt transfer from bottom left vertex. bottomright start bitblt transfer from bottom right vertex. bltcopyalternatep (format5) 31 24 23 16 15 0 bltcopyalternatep draw command reserved saddr sstride srys srxs daddr dstride drys drxs brsizey brsizex copies rectangle between two separate drawing frames for brsizex, specify at least 5 pixels (when direct color mode used) or 9 pixels (when indirect color mode used). commands: topleft start bitblt transfer from top left vertex. 92 loadtexturep (format6) 31 24 23 16 15 0 loadtexturep draw command count (pattern 0) (pattern 1) - - - (pattern n) loads texture or tile pattern into internal texture buffer memory supply a texture pattern to the internal texture buffer according to the current pattern size (txs/tis) and offset address (xbo). commands: loadtexture load texture pattern to internal texture buffer. loadtile load tile pattern to internal texture buffer. blttexturep (format5) 31 24 23 16 15 0 blttexturep draw command reserved srcaddr srcstride srcrectys srcrectxs brsizey brsizex destoffset loads texture or tile pattern into internal texture buffer memory from graphics memory supply a texture pattern to the internal texture buffer according to current pattern size (txs/tis) and offset address (xbo). for destoffset, specify the word-aligned byte address (16 bits) (bit 0 is always 0). for brsizex, specify at least 5 pixels (when direct color mode used) or 9 pixels (when indirect color mode used). commands: loadtexture load texture pattern into internal texture buffer. loadtile load tile pattern into internal texture buffer. 93 7 registers 7.1 description all the terms in this chapter are explained below: (1) register address indicates address of register (2) bit # indicates bit number (3) bit field name indicates name of each bit field in register (4) r/w indicates access attribute (read/write) of each field each sign shown in this section means the following: r0 0 always read at read. write access is dont care. w0 only 0 can be written r enable read rx enable read (read values undefined) rw enable read and write any data rw0 enable read and write 0 (5) default this section shows the reset defaults for each bit field. 94 7.1.1 host interface registers dtc (dma transfer count) register address hostbaseaddress + 00h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name reserved dtc r/w r0 rw default 0 don t care dtcr is a 32-bit wide register to set the dma data transfer count to either one long-word (32 bits) or eight long-word (32 bytes) units. this register is read/write enabled. when 1h is set, one data unit is transferred by dma. however, when 0h is set, it indicates the maximum transfer data count and 16m (16,777,216) data units are transferred. after dma transfer is started, the register value cannot be overwritten until dma transfer is completed. note: in the v832 mode, no setting is required for this register. dsu (dma set up) register address hostbaseaddress + 04h bit # 765432 10 bit field name reserved dam dbm dw r/w r0 rw rw rw default 0000 bit0 dw(dma word) sets dma transfer unit 0 1 long words (32 bytes) per dma transaction 1 8 long word (32 bits) per dma transaction (only sh4) dbm (dma bus request mode) selects dreq mode used when performing dma transfer in dual-address mode 0 dreq is irrelevant to the cycle steal mode or burst mode, and is not negated during dma transfer. bit1 1 dreq is irrelevant to the cycle steal mode or burst mode, and is negated when the MB86290A cannot receive data (that is, when ready cannot be returned immediately). when the MB86290A is ready to receive data, dreq is reasserted (when dma transfer is performed in the single-address mode, dreq is controlled automatically). bit2 dam(dma address mode) sets dma addressing mode 0 dual address mode 1 single address mode (sh4 only) 95 drm (dma request mask) register address hostbaseaddress + 05h bit # 76543210 bit field name reserved drm r/w r0 rw default 00 this register controls the dma request to the host cpu. setting 1 at this register tentatively masks the dma request. the dma request is restarted when 0 is set at this register. dst (dma status) register address hostbaseaddress + 06h bit # 76543210 bit field name reserved dst r/w r0 r default 00 this register indicates the dma status. dst is set to 1 during dma transfer. this state is cleared to 0 when the dma transfer is completed. dts (dma transfer stop) register address hostbaseaddress + 08h bit # 76543210 bit field name reserved dts r/w r0 rw default 00 this register suspends dma transfer. an ongoing dma transfer is suspended by setting dts to 1. lsta (displaylist transfer status) register address hostbaseaddress + 10h bit # 76543210 bit field name reserved lsta r/w r0 r default 00 96 this register indicates the displaylist transfer status from graphics memory. lsta is set to 1 while displaylist transfer is in progress. this status is cleared to 0 when displaylist transfer is completed drq (dma reqquest) register address hostbaseaddress + 18h bit # 76543210 bit field name reserved drq r/w r0 rw1 default 00 starts sending external dma request signal dma transfer using the external dma request handshake is triggered by setting drq to 1. the external dreq signal is not asserted when dma is masked by the drm register. this register cannot be set to 0. when dma transfer is completed, this status is cleared automatically to 0. ist (interrupt status) register address hostbaseaddress + 20h bit # 76543210 bit field name reserved fsync syncerr vsync cend cerr r/w r0 rw0 rw0 rw0 rw0 rw0 default 0 00000 this register indicates the current interrupt status. when an interrupt request to the host cpu is asserted, this register displays 1. the interrupt status is cleared by setting 0 at this register. bit 0 cerr (command error flag) draws command execution error interrupt bit 1 cend (command end) draws command complete interrupt bit 2 vsync (vertical sync.) vsync detection interrupt bit 3 fsync (frame sync.) indicates frame synchronization interrupt bit 4 syncerr (sync. error) indicates external synchronization error interrupt 97 imask (interrupt mask) register address hostbaseaddress + 24h bit # 76543210 bit field name reserved syncerrm fsyncm vsyncm cendm cerrm r/w r0 rw rw rw rw rw default 0 00000 this register masks interrupt requests. when the flag is set to 1, the respective event is masked so that no interrupt request is asserted to the host cpu when an event occurs. bit 0 cerrm (command error interrupt mask) masks draw command execution error interrupt bit 1 cendm (command interrupt mask) masks draw command complete interrupt bit 2 vsyncm (vertical sync. interrupt mask) masks vsync detection interrupt bit 3 fsyncm (frame sync. interrupt mask) masks frame synchronization interrupt bit 4 syncerrm (sync. error interrupt mask) masks external synchronization error interrupt srst (software reset) register address hostbaseaddress + 2ch bit # 76543210 bit field name reserved srst r/w r0 w1 default 00 this register controls software reset. when 1 is set at this register, a software reset is issued. lsa (displaylist source address) register address hostbaseaddress + 40h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name reserved lsa r/w r0 rw r0 default 0 don t care 0 this register sets the displaylist transfer source address. when displaylist is transferred from graphics memory, set the list start address. since the lowest two bits of this register are always set to 0, displaylist must be 4-byte aligned. the contents set at this register do not change until another value is set. 98 lco (displaylist count) register address hostbaseaddress + 44h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name reserved lco r/w r0 rw default 0 don t care this register sets the displaylist. transfer word count. when 1 is set, 1-word data is transferred. when 0 is set, it is considered to be the maximum number and 16m (16,777,216) words of data are transferred. the contents set at this register do not change until another value is set. lreq (displaylist transfer request) register address hostbaseaddress + 48h bit # 76543210 bit field name reserved lreq r/w r0 rw1 default 00 this register triggers displaylist transfer from the graphics memory. transfer is started by setting lreq to 1. displaylist. the displaylist is transferred from the graphics memory to the internal display list fifo. access to the display list fifo by the cpu or dma is prohibited while this transfer is in progress. 7.1.2 graphics memory interface registers mmr (memory i/f mode register) register address hostbaseaddress + fffch bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name reserve trrd trc trp tras trcd lowd rts raw asw cl r/w w0 rx rw rw rw rw rw rw rw rw rw rw default 00 don t care 11 1001 11 110 11 10 0111 10 1 011 this register controls the graphics memory interface mode setting. an appropriate value must be set at this register after reset (even if the default value is used). this register is not initialized by a software reset. bits 2-0 cl (cas latency) set cas latency cycles. set same value at mode register of sdram. 011 cl3 010 cl2 others prohibited 99 bit 3 asw (attached sdram bit width) sets data bus width of graphics memory interface 1 64 bit 0 32 bit bits 5-4 raw (row address width) set bit width of row address 00 14 bit 11 13 bit others prohibited bits 9-6 rts (refresh timing setting) set refresh interval 1010 1024 clocks 1001 512 clocks 1000 256 clocks 0111 128 clocks others prohibited 100 bits 11-10 lowd set last data output to next write command input latency 10 2 clocks others prohibited bits 13-12 trcd set bank active to cas latency 11 3 clocks 10 2 clocks others prohibited bits 16-14 tras set minimum bank active cycle 111 7 clocks 110 6 clocks 101 5 clocks others prohibited bits 18-17 trp set precharge to bank active wait time 11 3 clocks 10 2 clocks others prohibited bits 22-19 trc set refresh to bank active wait time 1010 10 clocks 1001 9 clocks 1000 8 clocks 0111 7 clocks others prohibited bits 24-23 trrd set bank active to next bank active wait time 11 3 clocks 10 2 clocks others prohibited 101 7.1.3 display control register dcm (display control mode) register address displaybaseaddress + 00h bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name cks reserve sc reserve eo reserve sof esy sync r/w rw r0 rw r0 rw r0 rw rw rw default 0 00 11110 00 0 0 0 0 00 this register controls the display mode. it is not initialized by a software reset. bits 1-0 sync (synchronize) set synchronization mode x0 non-interlace mode 11 interlace video mode bit 2 esy (external synchronize) sets external synchronization mode 0 disable 1 enable bit 3 sf (synchronize signal output format) sets active level of synchronization (vsync, hsync, csync) signals 0 low active 1 high active bit 5 eo (even/odd signal mode) defines eo signal output format 0 low level output at even frame, high level output at odd frame 1 high level output at even frame, low level output at odd frame bits 12-8 sc (scaling) define pre-scaling ratio to generate dot clock 00000 no pre-scaling 00001 1/2 00010 1/3 : : 11110 1/31 (default) 11111 1/32 bit 15 cks (clock source) selects source clock 0 internal pll output clock 1 dclki input 102 dce (display controller enable) register address displaybaseaddress + 02h bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name den reserved be me we ce r/w rw r0 rw rw rw rw default 0 0 0000 this register controls the video signal output and enables display of each layer. bit 0 ce (c layer enable) enables c-layer display 0 does not display c layer 1 displays c-layer bit 1 we (w layer enable) enables w-layer display 0 does not display w-layer 1 displays w layer bit 2 me (m layer enable) enables m layer display 0 does not display m layer 1 displays m layer bit 3 be (bl-layer enable) enables ml-layer display 0 does not display b layer 1 displays b layer bit 15 den (display enable) enables display 0 does not output display signal 1 outputs display signal 103 htp (horizontal total pixels) register address displaybaseaddress + 06h bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved htp r/w r0 rw default 0 don t care this register controls the total pixel count. setting + 1 is the total pixel count. hdp (horizontal display period) register address displaybaseaddress + 08h bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved hdp r/w r0 rw default 0 don t care this register controls the total horizontal display period in pixel clock units. setting + 1 is the pixel count for the display period. hdb (horizontal display boundary) register address displaybaseaddress + 0ah bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved hdb r/w r0 rw default 0 don t care this register controls the display period of the left partition in pixel raster units setting + 1 is the pixel count for the display period of the left partition. when the screen is not partitioned into right and left before display, set the same value as hdp. hsp (horizontal synchronize pulse position) register address displaybaseaddress + 0ch bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved hsp r/w r0 rw default 0 don t care this register controls the hsync pulse position in pixel clock unit. when the clock count since the start of the display period reaches setting + 1, the horizontal synchronization signal is asserted. 104 hsw (horizontal synchronize pulse width) register address displaybaseaddress + 0eh bit # 76543210 bit field name reserved hsw r/w r0 rw default 0 don t care this register controls the hsync pulse width in pixel-clock units. setting + 1 is the pulse width clock count. vsw (vertical synchronize pulse width) register address displaybaseaddress + 0fh bit # 76543210 bit field name reserved vsw r/w r0 rw default 0 don t care this register controls the vsync pulse width in raster units. setting + 1 is the pulse width raster count. vtr (vertical total rasters) register address displaybaseaddress + 12h bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved vtr r/w r0 rw default 0 don t care this register controls the total raster count. setting + 1 is the total raster count. for the interlace display, setting + 1.5 is the total raster count for 1 field; 2 setting + 3 is the total raster count for 1 frame (see section 8.3.2). vsp (vertical synchronize pulse position) register address displaybaseaddress + 14h bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved vsp r/w r0 rw default 0 don t care this register controls the vsync pulse position in raster units. the vertical synchronization pulse is asserted starting at the setting + 1-th raster relative to the display start raster. 105 vdp (vertical display period) register address displaybaseaddress + 16h bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved vtr r/w r0 rw default 0 don t care this register controls the vertical display period in raster unit. setting + 1 is the count of rasters to be displayed. wx (window position x) register address displaybaseaddress + 18h bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved wx r/w r0 rw default 0 don t care this register controls the horizontal position of the left edge of the window layer. set the left edge position of the window layer from the display field start edge in dot-clock units. wy (window position y) register address displaybaseaddress + 1ah bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved wy r/w r0 rw default 0 don t care this register controls the vertical position of the top edge of the window layer. set the top edge position of the window layer from the display field start edge in raster units. ww (window width) register address displaybaseaddress + 1ch bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved ww r/w r0 rw default 0 don t care this register controls the horizontal size (pixel count) of the window layer. do not specify 0. 106 wh (window height) register address displaybaseaddress + 1eh bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved wh r/w r0 rw default 0 don t care this register controls the vertical height (raster count) of the window layer. setting + 1 is the height. cm (c-layer mode) register address displaybaseaddress + 20h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name cc reserve reserve cw reserve ch r/w rw r0 r0 rw r0 rw default 0 0 0 don t care 0 don t care bits 11-0 ch (c-layer height) set height of console layer logical frame size in raster units. setting + 1 is the height. bits 23-16 cw (c-layer memory width) set width of console layer logical frame size in 64-byte units bit 31 cc (c-layer color mode) sets color mode used for console layer 0 indirect color mode (8 bits/pixel) 1 direct color mode (16 bits/pixel) coa(c-layer origin address) register address displaybaseaddress + 24h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name reserve coa r/w r0 rw r0 default 0 don t care 0000 this register controls the base address of the logical frame of the console layer. since the lowest 4 bits are fixed to 0, this address is 16-byte aligned. 107 cda (c-layer display address) register address displaybaseaddress + 28h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name reserve cda r/w r0 rw default 0 don t care this register controls the base address of the display field of the console layer. when the direct color mode is used, the lsb is fixed to 0 and this address is 2-byte aligned. cdx (c-layer display position x) register address displaybaseaddress + 2ch bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved cdx r/w r0 rw default 0 don t care set the display start position (x-coordinate) for the c layer in pixel units relative to the origin of the logical frame. cdy (c-layer display position y) register address displaybaseaddress + 2eh bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved cdy r/w r0 rw default 0 don t care set the display start position (y-coordinate) for the c-layer in pixel units relative to the origin of the logical frame. wm (w-layer mode) register address displaybaseaddress + 30h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name reserve ww reserve r/w r0 rw r0 default 0 don t care 0 bits 21-16 ww(w-layer memory width) set width of window layer logical frame size in 64-byte units. wc (w-layer color mode) sets color mode for w-layer 0 indirect color (8 bits/pixel) mode bit 31 1 direct color (16 bits/pixel) mode 108 woa (w-layer origin address) register address displaybaseaddress + 34h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name reserve woa r/w r0 rw r0 default 0 don t care 0000 this register controls the base address of the logical frame of the window layer. since the lowest 4-bits are fixed to 0, this address is 16-byte aligned. wda (w-layer display address) register address displaybaseaddress + 38h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name reserve wda r/w r0 rw default 0 don t care this register controls the base address of the display field of the window layer. since only the direct color mode is applicable to the window layer, the lsb is fixed to 0 and this address is 2-byte aligned. mlm (ml-layer mode) register address displaybaseaddress + 40h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name mlc mlflp reserve mlw reserve mlh r/w rw r0 r0 rw r0 rw default 0 0 0 don t care 0 don t care bits 11-0 mlh (ml-layer height) set height of middle left (ml) layer logical frame size in raster units. setting + 1 is the height. bits 23-16 mlw (ml-layer memory width) set width of middle left (ml) layer logical frame size in 64-byte units bits 30-29 mlflp (ml-layer flip mode) set flipping mode for middle left (ml) layer 00 display frame 0 01 display frame 1 10 switch frame 0 and 1 back and forth 11 reserved bit 31 mlc (ml-layer color mode) sets color mode for middle left (ml) layer 0 indirect color mode (8 bits/pixel) 1 direct color mode (16 bits/pixel) 109 mloa0 (ml-layer origin address 0) register address displaybaseaddress + 44h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name reserve mloa0 r/w r0 rw r0 default 0 don t care 0000 this register controls the base address of the logical frame (frame0) of the middle left (ml) layer. since the lowest 4 bits are fixed to 0, this address is 16-byte aligned. mlda0 (ml-layer display address 0) register address displaybaseaddress + 48h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name reserve mlda0 r/w r0 rw default 0 don t care this register controls the base address of the middle left (ml) layer display field in frame0. when the direct color mode is used, the lsb is fixed to 0 and this address is 2-byte aligned. mloa1 (ml-layer origin address 1) register address displaybaseaddress + 4ch bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name reserve mloa1 r/w r0 rw r0 default 0 don t care 0000 this register controls the base address of the logical frame (frame1) of the middle left (ml) layer. since the lowest 4-bits are fixed to 0, this address is 16-byte aligned. mlda1 (ml-layer display address 1) register address displaybaseaddress + 50h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name reserve mlda1 r/w r0 rw default 0 don t care this register controls the base address of the middle left (ml) layer display field in frame1. when the direct color mode is used, the lsb is fixed to 0 and this address is 2-byte aligned. mldx (ml-layer display position x) register address displaybaseaddress + 54h bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved mldx r/w r0 rw default 0 don t care 110 set the display start position (x-coordinate) for the ml layer in pixel units relative to the origin of the logical frame. mldy (ml-layer display position y) register address displaybaseaddress + 56h bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved mldy r/w r0 rw default 0 don t care set the display start position (y-coordinate) for the ml layer in pixel units relative to the origin of the logical frame. mrm (mr-layer mode) register address displaybaseaddress + 58 bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name mrc mrflp reserve mrw reserve mrh r/w rw r0 r0 rw r0 rw default 0 0 0 don t care 0 don t care bits 11-0 mrh (mr-layer height) set height of middle right (mr) layer logical frame size in raster units. setting + 1 is the height. bits 23-16 mrw (mr-layer memory width) set width of middle right (mr) layer logical frame size in 64-byte units bits 30-29 mrflp (mr-layer flip mode) set flipping mode for middle right (mr) layer 00 display frame 0 01 display frame 1 10 switch frame 0 and 1 back and forth 11 reserved bit 31 mrc (mr-layer color mode) sets color mode for middle right (mr) layer 0 indirect color mode (8 bits/pixel) 1 direct color mode (16 bits/pixel) 111 mroa0 (mr-layer origin address 0) register address displaybaseaddress + 5ch bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name reserve mroa0 r/w r0 rw r0 default 0 don t care 0000 this register controls the base address of the logical frame (frame0) of the middle right (mr) layer. since the lowest 4 bits are fixed to 0, this address is 16-byte aligned. mrda0 (mr-layer display address 0) register address displaybaseaddress + 60h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name reserve mrda0 r/w r0 rw default 0 don t care this register controls the base address of the middle left (ml) layer display field in frame0. when the direct color mode is used, the lsb is fixed to 0 and this address is 2-byte aligned. mroa1 (mr-layer origin address 1) register address displaybaseaddress + 64h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name reserve mroa1 r/w r0 rw r0 default 0 don t care 0000 this register controls the base address of the logical frame (frame1) of the middle right (mr) layer. since the lowest 4 bits are fixed to 0, this address is 16-byte aligned. mrda1 (mr-layer display address 1) register address displaybaseaddress + 68h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name reserve mrda1 r/w r0 rw default 0 don t care this register controls the base address of the middle right (mr) layer display field in frame1. when the direct color mode is used, the lsb is fixed to 0 and this address is 2-byte aligned. mrdx (mr-layer display position x) register address displaybaseaddress + 6ch bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved mrdx r/w r0 rw default 0 don t care 112 set the display start position (x-coordinate) for the mr layer in pixel units relative to the origin of the logical frame. mrdy (mr-layer display position y) register address displaybaseaddress + 6eh bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved mrdy r/w r0 rw default 0 don t care set the display start position (y-coordinate) for the mr layer in pixel units relative to the origin of the logical frame. blm (bl-layer mode) register address displaybaseaddress + 70h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name blc blflp reserve blw reserve blh r/w rw r0 r0 rw r0 rw default 0 0 0 don t care 0 don t care bits 11-0 blh (bl-layer height) set height of base left (bl) layer logical frame size in raster units. setting + 1 is the height. bits 23-16 blw (bl-layer memory width) set width of base left (bl) layer logical frame size in 64-byte units bits 30-29 blflp (bl-layer flip mode) set flipping mode for base left (bl) layer 00 display frame 0 01 display frame 1 10 switch frame 0 and 1 back and forth 11 reserved bit 31 blc (bl-layer color mode) sets color mode for base left (bl) layer 0 indirect color mode (8 bits/pixel) 1 direct color mode (16 bits/pixel) 113 bloa0 (bl-layer origin address 0) register address displaybaseaddress + 74h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name reserve bloa0 r/w r0 rw r0 default 0 don t care 0000 this register controls the base address of the logical frame (frame0) of the base left (bl) layer. since the lowest 4 bits are fixed to 0, this address is 16- byte aligned. blda0 (bl-layer display address 0) register address displaybaseaddress + 78h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name reserve blda0 r/w r0 rw default 0 don t care this register controls the base address of the base left (bl) layer display field in frame0. when the direct color mode is used, the lsb is fixed to 0 and this address is 2-byte aligned. bloa1 (bl-layer origin address 1) register address displaybaseaddress + 7ch bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name reserve bloa1 r/w r0 rw r0 default 0 don t care 0000 this register controls the base address of the logical frame (frame1) of the base left (bl) layer. since the lowest 4 bits are fixed to 0, this address is 16- byte aligned. blda1 (bl-layer display address 1) register address displaybaseaddress + 80h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name reserve blda1 r/w r0 rw default 0 don t care this register controls the base address of the base left (bl) layer display field in frame1. when the direct color mode is used, the lsb is fixed to 0 and this address is 2-byte aligned. bldx (bl-layer display position x) register address displaybaseaddress + 84h bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved bldx r/w r0 rw default 0 don t care 114 set the display start position (x-coordinate) for the bl layer in pixel units relative to the origin of the logical frame. bldy (bl-layer display position y) register address displaybaseaddress + 86h bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved bldy r/w r0 rw default 0 don t care set the display start position (y-coordinate) for the bl-layer in pixel units relative to the origin of the logical frame. brm (br-layer mode) register address displaybaseaddress + 88h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name brc brflp reserve brw reserve brh r/w rw r0 r0 rw r0 rw default 0 0 0 don t care 0 don t care bits 11-0 brh (br-layer height) set height of base right (br) layer logical frame size in raster units. setting + 1 is the height. bits 23-16 brw (br-layer memory width) set width of base right (br) layer logical frame size in 64-byte units bits 30-29 brflp (br-layer flip mode) set flipping mode for base right (br) layer 00 display frame 0 01 display frame 1 10 switch frame 0 and 1 back and forth 11 reserved bit 31 brc (br-layer color mode) sets color mode for base right (br) layer 0 indirect color mode (8 bits/pixel) 1 direct color mode (16 bits/pixel) 115 broa0 (br-layer origin address 0) register address displaybaseaddress + 8ch bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name reserve broa0 r/w r0 rw r0 default 0 don t care 0000 this register controls the base address of the logical frame (frame0) of the base right (br) layer. since the lowest 4 bits are fixed to 0, this address is 16-byte aligned. brda0 (br-layer display address 0) register address displaybaseaddress + 90h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name reserve brda0 r/w r0 rw default 0 don t care this register controls the base address of the base right (br) layer display field in frame0. when the direct color mode is used, the lsb is fixed to 0 and this address is 2-byte aligned. broa1 (br-layer origin address 1) register address displaybaseaddress + 94h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name reserve broa1 r/w r0 rw r0 default 0 don t care 0000 this register controls the base address of the logical frame (frame1) of the base right (br) layer. since the lowest 4 bits are fixed to 0, this address is 16-byte aligned. brda1 (br-layer display address 1) register address displaybaseaddress + 98h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name reserve brda1 r/w r0 rw default 0 don t care this register controls the base address of base right (br) layer display field in frame1. when the direct color mode is used, the lsb is fixed to 0 and this address is 2-byte aligned. brdx (br-layer display position x) register address displaybaseaddress + 9ch bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved brdx r/w r0 rw default 0 don t care 116 set the display start position (x-coordinate) for the br layer in pixel units relative to the origin of the logical frame. brdy (br-layer display position y) register address displaybaseaddress + 9eh bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved brdy r/w r0 rw default 0 don t care t set the display start position (y-coordinate) for the br layer in pixel units relative to the origin of the logical frame. cutc (cursor transparent control) register address displaybaseaddress + a0h bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved cuzt cutc r/w r0 rw rw default 0 don t care don t care bits 7-0 cutc (cursor transparent code) set transparency color code bit 8 cuzt (cursor zero transparency) defines treatment of color code 0 0 code 0 transparency color 1 code 0 not transparency color 117 cpm (cursor priority mode) register address displaybaseaddress + a2h bit # 76543210 bit field name reserved cen1 cen0 reserved cuo1 cuo0 r/w r0 rw rw r0 rw rw default 000000 this register controls the display priority of cursors. cursor 0 is always prioritized to cursor 1. bit 0 cuo0 (cursor overlap 0) sets display priority between cursor 0 and pixels of console layer 0 put cursor 0 at bottom of console layer. 1 put cursor 0 at top of console layer. bit 1 cuo1 (cursor overlap 1) sets display priority between cursor 1 and pixels of console layer 0 put cursor 1 at bottom of console layer. 1 put cursor 1 at top of console layer. bit 4 cen0 (cursor enable 0) sets display enable of cursor 0 0 disable 1 enable bit 5 cen1 (cursor enable 1) sets display enable of cursor 1 0 disable 1 enable cuoa0 (cursor-0 origin address) register address displaybaseaddress + a4h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name reserve cuoa0 r/w r0 rw r0 default 0 don t care 0000 this register controls the start address of the cursor-0 pattern. since the lowest 4 bits are fixed to 0, this address is 16-byte aligned. 118 cux0 (cursor-0 x position) register address displaybaseaddress + a8h bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved cux0 r/w r0 rw default 0 don t care this register controls the horizontal position of the cursor-0 pattern left edge. set the left-edge position of the cursor-0 pattern from the start edge of the display field in dot-clock units. cuy0 (cursor-0 y position) register address displaybaseaddress + aah bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved cuy0 r/w r0 rw default 0 don t care this register controls the vertical position of the cursor-0 pattern top edge. set the top edge position of the cursor-0 pattern from the start edge of the display field in raster units. cuoa1 (cursor-1 origin address) register address displaybaseaddress + ach bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name reserve cuoa1 r/w r0 rw r0 default 0 don t care 0000 this register controls the start address of the cursor-1 pattern. since the lowest 4 bits are fixed to 0, this address is 16-byte aligned. cux1 (cursor-1 x position) register address displaybaseaddress + b0h bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved cux1 r/w r0 rw default 0 don t care this register controls the horizontal position of the cursor-1 pattern left edge. set the left edge position of the cursor-0 pattern from the start edge of the display field in dot-clock units. 119 cuy1 (cursor-1 y position) register address displaybaseaddress + b2h bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved cuy1 r/w r0 rw default 0 don t care this register controls the vertical position of the cursor-1 pattern top edge. set the top edge position of the cursor-0 pattern from the start edge of the display field in raster units. bratio (blend ratio) register address displaybaseaddress + b4h bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name brs reserved bratio reserved r/w rw r0 rw r0 default 0 0 0 0000 this register controls the blending ratio for console layer pixels when using the blending mode. bits 7-4 bratio (blend ratio) set blending ratio 0000 coefficient = 0 0001 coefficient = 1/16 : : 1111 coefficient = 15/16 bit 15 brs (blend ratio select) selects formula for alpha blending 0 (c-layer color x coefficient) + (combination color of w/m/b layers x (1 - coefficient)) 1 (c-layer color x (1 - coefficient)) + (combination color of w/m/b layers x coefficient) bmode (blend mode) register address displaybaseaddress + b6h bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved reserve blend r/w r0 r0 rw default 000 this register controls the console layer overlay options. the color set as a transparent color is irrelevant to the alpha bit and blend processing is not performed. bit 0 blend overlays mode between c and b/m/w 0 simple priority mode (c-layer given priority at all times) 1 blending mode 120 when performing blend processing, specify the blend mode for this bit; alpha must be enabled previously in c-layer display data. in the direct color mode, specify alpha for the most significant bit. in the indirect color mode, specify alpha for the most significant bit of pallet data. keyc (key color) register address displaybaseaddress + b8h bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name kyen kyc r/w rw rw default 0 don t care bits 14-0 kyc (key color) set key color for chroma-key operation. bits 7-0 used in indirect color mode. bits 7-0 are used when the indirect color mode (8 bits/pixel) and the chroma key mode are set to the c-layer color. bit 15 kyen (chroma-key enable) enables/disables chroma-key operation 0 disable chroma-key operation (h always output from gv pin). 1 enable chroma-key operation. ckm (chroma key mode) register address displaybaseaddress + bah bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved kcs r/w r0 rw default 00 bit 0 kcs (key color select) selects key color as c-layer color or display color 0 set key color as display color. 1 set key color as c-layer color. (see section 5.5 .) 121 ctc (c-layer transparent control) register address displaybaseaddress + bch bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name czt ctc r/w rw rw default 0 don t care this register controls the transparent color setting for the c layer. the color defined as a transparent color by this register is treated as a transparent color even in the blending mode. when both ctc and czt are set to 0, color 0 is displayed in black (not transparent). bits 14-0 ctc (c-layer transparent color) set color code of transparent color used in console layer. bits 7-0 used in indirect color mode. bit 15 czt (c-layer zero transparency) sets treatment for code 0 in console layer 0 code 0 not transparent color 1 code 0 transparent color mrtc (mr-layer transparent control) register address displaybaseaddress + c0h bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name mrzt mrtc r/w rw rw default 0 don t care this register controls the transparent color setting for the mr-layer. when both mrtc and mrzt are set to 0, color 0 is displayed in black (not transparent). bits 14-0 mrtc (mr-layer transparent color) set color code of transparent color used in mr-layer. bits 7-0 used in indirect color mode. bit 15 mrzt (mr-layer zero transparency) sets treatment for code 0 in mr-layer 0 code 0 not transparent color 1 code 0 transparent color 122 mltc (ml-layer transparent control) register address displaybaseaddress + c2h bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name mlzt mltc r/w rw rw default 0 don t care this register controls the transparent color setting for the ml-layer. when both mltc and mlzt are set to 0, color 0 is displayed in black (not transparent). bits 14-0 mltc (ml-layer transparent color) set color code of transparent color used in ml-layer. bits 7-0 used in indirect color mode. bit 15 mlzt (ml-layer zero transparency) sets treatment for code 0 in ml-layer 0 code 0 not transparent color 1 code 0 transparent color cpal0-255 (c-layer pallet 0-255) register address displaybaseaddress + 400h -- displaybaseaddress + 7ffh bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name argb r/w rw r0 rw r0 rw r0 rw r0 default don t care 0000000 don t care 00 don t care 00 don t care 00 these are color pallet registers for console layer and cursors. in the indirect color mode, a color code in the display field indicates the pallet register number (pallet entry number), and the color information set in that entry is applied as the display color of that pixel. bits 7-2 b (blue) set blue color element bit 15-10 g (green) set green color element bits 23-18 r (red) set red color element bit 31 a (alpha) when blending mode used, color blended with b/m/w layer pixel color according to blending ratio for pixel of c layer with bit = 1. alpha blending mode ignored when used as cursor color. 123 mbpal0-255 (m-layer and b-layer pallet 0-255) register address displaybaseaddress + 800h -- displaybaseaddress + bffh bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 87654 3 2 1 0 bit field name reserve r g b r/w r0 rw r0 rw r0 rw r0 default 0 don t care 00 don t care 00 don t care 00 these are color pallet registers for middle and base layers. in the indirect color mode, a color code in the display field indicates the pallet register number (pallet entry number), and the color information set in that entry is applied as the display color of that pixel. bits 7-2 b (blue) set blue color element bits 15-10 g (green) set green color element bits 23-18 r (red) set red color element 124 7.1.4 draw control registers ctr (control register) register address drawbaseaddress + 400h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name fo pe ce fcnt nf ff fe ss ds ps r/w rw rw rw r r r r rrr default 0 0 0 100000 0 0 1 00 00 00 this register indicates draw flags and status. bits 24-22 are not cleared until 0 is set. bits 1-0 ps (pixel engine status ) indicate status of pixel engine unit 00 idle 01 busy 10 reserved 11 reserved bits 5-4 ds (dda status) indicate status of dda 00 idle 01 busy 10 reserved 11 reserved bits 9-8 ss (setup status) indicate status of set up unit 00 idle 01 busy 10 reserved 11 reserved bit 12 fe (fifo empty) indicates status of display list fifo 0 valid data 1 no valid data bit 13 ff (fifo full) indicates fullness of display list fifo 0 not full 1full bit 14 nf (fifo near full) indicates entries of display list fifo 0 empty entries equal to or more than half 125 1 empty entries less than half bits 20-15 fcnt(fifo counter) indicate number of empty entries (0: full - 32: empty) bit 22 ce (display list command error) indicates command error detection 0normal 1 command error detected bit 23 pe (display list packet code error) indicates packet code error detection 0normal 1 packet code error detected bit 24 fo (fifo overflow) indicates fifo overflow status 0normal 1 fifo overflow detected ifsr (input fifo status register) register address drawbaseaddress + 404h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name nf ff fe r/w r r r default 00 1 this is a miller register for bits 14-12 of the ctr register. ifcnt (input fifo counter) register address drawbaseaddress + 408h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name fcnt r/w r default 100000 this is a miller register for bits 19-15 of the ctr register. sst (setup engine status) register address drawbaseaddress + 40ch bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name ss r/w r default 00 this is a miller register for bits 9-8 of the ctr register. 126 dst (dda status) register address drawbaseaddress + 410h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name ds r/w rw default 00 this is a miller register for bits 5-4 of the ctr register. pst (pixel engine status) register address drawbaseaddress + 414h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name ps r/w rw default 00 this is a miller register for bits 1-0 of the ctr register. est (error status) register address drawbaseaddress + 418h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name fo pe ce r/w rw rw rw default 00 0 this is a miller register for bits 24-22 of the ctr register. 127 7.1.5 draw mode parameter registers when wirte to the registers, use the setregister command. the registers cannot be accessed from the cpu. mdr0 (mode register for miscellaneous) register address drawbaseaddress + 420h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name cf cy cx bsv bsh r/w rw rw rw rw rw default 0000000 bits 1-0 bsh (bitmap scale horizontal) set horizontal zoom ratio of bitmap draw 00 x1 01 x2 10 x1/2 01 reserved bits 3-2 bsv (bitmap scale vertical) set vertical zoom ratio of bitmap draw 00 x1 01 x2 10 x1/2 01 reserved bit 8 cx (clip x enable) sets x-coordinate clipping mode 0 disable 1 enable bit 9 cy (clip y enable) sets y-coordinate clipping mode 0 disable 1 enable bit 15 cf (color format) sets drawing color format of current draw frame 0 indirect color mode (8 bits/pixel) 1 direct color mode (16 bits/pixel) 128 mdr1 (mode register for line) register address drawbaseaddress + 424h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 98 7 6 5 4 3 2 10 bit field name lw bl log bm zw zcl zc r/w rw rw rw rw rw rw rw default 00000 0 0011 0 0 0000 0 this register controls the mode of line draw and pixel plot. bit 2 zc (z compare mode) sets z comparison mode 0 disable 1 enable bits 5-3 zcl (z compare logic) select type of z comparison 000 never 001 always 010 less 011 lequal 100 equal 101 gequal 110 greater 111 notequal bit 6 zw (z write mask) sets zwritemask 0 compare z values and overwrite result to z buffer. 1 compare z values and do not overwrite to z buffer. bits 8-7 bm (blend mode) set blend mode 00 normal (source copy) 01 alpha blending 10 logical calculation enable 11 reserved 129 bits 12-9 log (logical operation) set type of logical calculation 0000 clear 0001 and 0010 and reverse 0011 copy 0100 and inverted 0101 nop 0110 xor 0111 or 1000 nor 1001 equiv 1010 invert 1011 or reverse 1100 copy inverted 1101 or inverted 1110 nand 1111 set bit 19 bl (broken line) selects line type 0 solid line 1 broken line bits 28-24 lw (line width) set line width 00000 1 pixel 00001 2 pixels : : 11111 32 pixels 130 mdr2 (mode register for polygon) register address drawbaseaddress + 428h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 98 7 6 5 4 3 2 10 bit field name tt log bm zw zcl zc sm r/w rw rw rw rw rw rw rw default 00 0011 0 0 0000 0 0 this register controls the polygon draw mode. bit 0 sm (shading mode) sets shading mode 0 flat shading 1 gouraud shading bit 2 zc (z compare mode) sets z comparison mode 0 disable 1 enable bits 5-3 zcl (z compare logic) select type of z comparison 000 never 001 always 010 less 011 lequal 100 equal 101 gequal 110 greater 111 notequal bit 6 zw (z write mask) sets zwritemask 0 compare z values and overwrite result to z buffer 1 compare z values and do not overwrite result to z buffer bits 8-7 bm (blend mode) set blend mode 00 normal (source copy) 01 alpha blending 10 logical calculation enable 11 reserved 131 bits 12-9 log (logical operation) set type of logical calculation 0000 clear 0001 and 0010 and reverse 0011 copy 0100 and inverted 0101 nop 0110 xor 0111 or 1000 nor 1001 equiv 1010 invert 1011 or reverse 1100 copy inverted 1101 or inverted 1110 nand 1111 set bits 29-28 tt (texture-tile select) select texture or tile pattern 00 not used 01 enable tiling operation 10 enable texture mapping 11 reserved 132 mdr3 (mode register for texture) register address drawbaseaddress + 42ch bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 210 bit field name tab tbl tws twt tf tc tbu r/w rw rw rw rw rw rw rw default 00 00 00 00 0 0 0 this register controls the texture mapping mode. bit 0 tbu (texture buffer) selects texture memory (internal buffer always used in tiling) 0 external graphics memory 1 internal texture buffer bit 3 tc (texture coordinates correct) controls perspective correction mode 0 disable 1 enable bit 5 tf (texture filtering) sets texture filtering mode 0 point sampling 1 bi-linear filtering bits 9-8 twt (texture wrap t) set texture t-coordinate wrapping mode 00 repeat 01 cramp 10 border 11 reserved bits 11-10 tws (texture wrap s) set texture s coordinate wrapping mode 00 repeat 01 cramp 10 border 11 reserved bits 17-16 tbl (texture blend mode) set texture blending mode 00 decal 01 modulate 10 stencil 11 reserved bits 21-20 tab (texture alpha blend mode) set texture alpha blending mode. the stencil alpha mode is used only when the bm bits in the mdr1 register are set to 01 (alpha blending). if any other mode is set at the bm bit field, the stencil alpha mode is treated as the stencil mode. 00 normal 01 stencil 10 stencil alpha 11 reserved 133 mdr4 (mode register for blt) register address drawbaseaddress + 430h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 65432 1 0 bit field name log bm ti r/w rw rw rw default 0011 00 0 this register controls the bitblt. mode. bits 8-7 bm (blend mode) set blend mode 00 normal (source copy) 01 reserved 10 logical calculation enable 11 reserved bits 12-9 log (logical operation) set logical calculation type 0000 clear 0001 and 0010 and reverse 0011 copy 0100 and inverted 0101 nop 0110 xor 0111 or 1000 nor 1001 reserved 1010 invert 1011 or reverse 1100 copy inverted 1101 or inverted 1110 nand 1111 set 134 fbr (frame buffer base) register address drawbaseaddress + 440h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name fbase r/w rw r0 default don t care 0 this register controls the base address of the drawing frame memory. xres (x resolution) register address drawbaseaddress + 444h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name xres r/w rw default don t care this register controls the drawing frame horizontal resolution. zbr (z-buffer base) register address drawbaseaddress + 448h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name zbase r/w rw r0 default don t care 0 this register controls the z-buffer base address. tbr (texture memory base) register address drawbaseaddress + 44ch bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name tbase r/w rw r0 default don t care 0 this register controls the texture memory base address. pfbr (2d polygon flag-buffer base) register address drawbaseaddress + 450h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name pfbase r/w rw r0 default don t care 0 this register controls the polygon flag buffer base address. 135 cxmin (clip x minimum) register address drawbaseaddress + 454h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name clipxmin r/w rw default don t care this register controls the clip frame minimum x position. cxmax (clip x maximum) register address drawbaseaddress + 458h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name clipxmax r/w rw default don t care this register controls the clip frame maximum x position. cymin (clip y minimum) register address drawbaseaddress + 45ch bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name clipymin r/w rw default don t care this register controls the clip frame minimum y position. cymax (clip y maximum) register address drawbaseaddress + 460h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name clipymax r/w rw default don t care this register controls the clip frame maximum y position. 136 txs (texture size) register address drawbaseaddress + 464h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name txsn txsm r/w rw rw default 100000000 100000000 this register controls the texture size (m, n). bits 8-0 txsm (texture size m) set horizontal texture size. any power of 2 between 4 and 256 can be used. values that are not a power of 2 cannot be used. 000000100 m=4 000001000 m=8 000010000 m=16 000100000 m=32 001000000 m=64 010000000 m=128 100000000 m=256 others prohibited bits 24-16 txsn (texture size n) set vertical texture size. any power of 2 between 4 and 256 can be used. values that are not a power of 2 cannot be used. 000000100 n=4 000001000 n=8 000010000 n=16 000100000 n=32 001000000 n=64 010000000 n=128 100000000 n=256 others prohibited 137 tis (tile size) register address drawbaseaddress + 468h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name tisn tism r/w rw rw default 1000000 1000000 this register controls the tile size (m, n). bits 6-0 tism (title size m) set horizontal tile pattern size. any power of 2 between 4 and 64 can be used. values that are not a power of 2 cannot be used. 0.000100 m=4 0001000 m=8 0010000 m=16 0100000 m=32 1000000 m=64 others prohibited bits 22-16 tisn (title size n) set vertical tile pattern size. any power of 2 between 4 and 643 can be used. values that are not a power of 2 cannot be used. 0000100 n=4 0001000 n=8 0010000 n=16 0100000 n=32 1000000 n=64 others prohibited toa (texture buffer offset address) register address drawbaseaddress + 46ch bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name xbo r/w rw default don t care this register controls the texture buffer offset address of. by using this offset value, multiple texture patterns can be used and referred to the texture buffer memory. specify the word-aligned byte address (16 bits). (bit 0 is always 0.) 138 fc (foreground color) register address drawbaseaddress + 480h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name fgc r/w rw default 0 this register controls the drawing frame foreground color. this color is used for the object color of flat shading and foreground color of bitmap draw and broken line draw. at bitmap drawing, all bits set to 1 are drawn in the color set at this register. bits 15-0 fgc (foreground color) set foreground color value. in the indirect color mode, the lower 8 bits (bits 7-0) are used. bc (background color) register address drawbaseaddress + 484h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name bt bgc r/w rw rw default 00 this register controls the drawing frame background color. this color is used for the background color of bitmap draw and broken line draw. at bitmap drawing, all bits set to 1 are drawn in the color set at this register. bits 14-0 bgc (background color) set background color value. in the indirect color mode, the lower 8 bits (bit 7-0) are used. bit 15 bt (background transparency) sets transparent mode of background color 0 draw background in color used in bgc field. 1 dont draw background (use current color). 139 alf (alpha factor) register address drawbaseaddress + 488h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name a r/w rw default 0 this register controls the alpha blending ratio. blp (broken line pattern) register address drawbaseaddress + 48ch bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name blp r/w rw default 0 this register controls the broken-line pattern. the bit 1 set in the broken- line pattern is drawn in the foreground color and bit 0 is drawn in the background color. the actual line pattern is pasted from msb to lsb to the line to be drawn. if the length of the applied line is longer than 32 bits, the same line pattern is wrapped around in 32-bit units. the current position (bit #) of the line pattern used for the line is set in the blpo register. tbc (texture border color) register address drawbaseaddress + 494h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 bit field name -bc r/w r0 rw default 00 this register controls the texture mapping border color. bits 14-0 bc (border color) set border color of texture mapping. only the direct color mode is used. 140 blpo (broken line pattern offset) register address drawbaseaddress + 3e0h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 98765 4 321 0 bit field name bcr r/w rw default 11111 this register controls the start bit position of the broken line pattern set to blp registers, for broken line drawing. the lowest 5 bits contain the bit number of the broken line pattern. this value is decremented at each pixel draw. broken line drawing can be started from any position of the specified broken line pattern by setting any number at this register. 141 7.1.6 triangle draw registers each register is used by the drawing commands. the registers cannot be accessed from the cpu or by using the setregister command. (xy-coordinate register) register address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ys 0000h s s s s int 0 xs 0004h s s s s int frac dxdy 0008h s s s s int frac xus 000ch s s s s int frac dxudy 0010h s s s s int frac xls 0014h s s s s int frac dxldy 0018h s s s s int frac usn 001bh 0 0 0 0 int 0 lsn 0020h 0 0 0 0 int 0 address offset from drawbaseaddress s sign bit or sign extension 0 not used or 0 extension int integer or integer part of fixed point data frac fraction part of fixed point data sets (x, y) coordinates for triangle drawing ys y-coordinate start position of long side xs x-coordinate start position of long side dxdy x dda value of long side xus x-coordinate start position of top side dxudy x dda value of top side xls x-coordinate start position of bottom side dxldy x dda value of lower side usn number of spans (rasters) of top triangle. if this value is 0, the top triangle is not drawn. lsn number of spans (rasters) of bottom triangle. if this value is 0, the bottom triangle is not drawn. (color register) register address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rs 0040h 0 0 0 0 0 0 0 0 int frac drdx 0044h s s s s s s s s int frac drdy 0048h s s s s s s s s int frac gs 004ch 0 0 0 0 0 0 0 0 int frac dgdx 0050h s s s s s s s s int frac dgdy 0054h s s s s s s s s int frac bs 0058h 0 0 0 0 0 0 0 0 int frac dbdx 005ch s s s s s s s s int frac dbdy 0060h s s s s s s s s int frac address offset from drawbaseaddress s sign bit or sign extension 0 not used or 0 extension int integer or integer part of fixed point data frac fraction part of fixed point data 142 sets color parameters for triangle drawing. these parameters are used in the gouraud shading mode. rs r value at (xs, ys, zs) of long side drdx r dda value of horizontal way drdy r dda value of long side gs g value at (xs, ys, zs) of long side dgdx g dda value of horizontal way dgdy g dda value of long side bs b value at (xs, ys, zs) of long side dbdx b dda value of horizontal way dbdy b dda value of long side (z-coordinate register) register address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 zs 0080h 0 int frac dzdx 0084h s int frac dzdy 008ch s int frac address offset from drawbaseaddress s sign bit or sign extension 0 not used or 0 extension int integer or integer part of fixed point data frac fraction part of fixed point data sets z-coordinate for 3d triangle drawing zs z-coordinate start position of long side dzdx z dda value of horizontal way dzdy z dda value of long side (texture coordinate register) register address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ss 00c0h s s s s s s s int frac dsdx 00c4h s s s s s s s int frac dsdy 00c8h s s s s s s s int frac ts 00cch s s s s s s s int frac dtdx 00d0h s s s s s s s int frac dtdy 00d4h s s s s s s s int frac qs 00d8h 0 0 0 0 0 0 0 int frac dqdx 00dch s s s s s s s int frac dqdy 00e0h s s s s s s s int frac address offset from drawbaseaddress s sign bit or sign extension 0 not used or 0 extension int integer or integer part of fixed point data frac fraction part of fixed point data 143 sets texture coordinate parameters for triangle drawing ss s-coordinate of texture at (xs, ys, zs) of long side dsdx s dda value of horizontal way dsdy s dda value of long side ts t-coordinate of texture at (xs, ys, zs) of long side dtdx t dda value of horizontal way dtdy t dda value of long side qs q (perspective correction value) of texture at (xs, ys, zs) of long side dqdx q dda value of horizontal way dqdy q dda value of long side 144 7.1.7 line draw registers each register is used by the drawing commands. the registers cannot be accessed from the cpu or by using the setregister command. (coordinate register) register address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lpn 0140h 0 0 0 0 int 0 lxs 0144h s s s s int frac lxde 0148h s s s s s s sssssssssint frac lys 014ch s s s s int frac lyde 0150h s s s s s s sssssssssint frac lzs 0154h s int frac lzde 0158h s int frac address offset from drawbaseaddress s sign bit or sign extension 0 not used or 0 extension int integer or integer part of fixed point data frac fraction part of fixed point data sets coordinate parameters for line drawing lpn pixel length of line (*1) lxs x-coordinate position of line draw start vertex (-pai/4 ? line angle ? pai/4) set truncated integer value of x-coordinate. (other than above) set current integer part of fixed point x-coordinate data. lxde line angle data for x axis (-pai/4 ? /lqh dqjoh ? pai/4) increment or decrement according to drawing direction. (other than above) set fraction part of dx/dy. lys y-coordinate position of line pai draw start vertex (-pai/4 ? line angle ? pai/4) set current integer part of fixed point y-coordinate data. (other than above) set truncated integer value of y-coordinate. lyde line angle data for y-axis (-pai/4 ? line angle ? pai/4) set fraction part of dy/dx. (other than above) increment or decrement according to drawing direction. lzs z-coordinate position of line draw start vertex lzde z angle (*1) if -pai/4 ? line angle ? pai/4: horizontal length of line in pixel units other than above: vertical length of line in pixel units 145 (color register) register address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 lrs 015ch 0 0 0 0 0 0 0 0 int frac lrde 0160h s s s s s s s s int frac lgs 0164h 0 0 0 0 0 0 0 0 int frac lgde 0168h s s s s s s s s int frac lbs 016ch 0 0 0 0 0 0 0 0 int frac lbde 0170h s s s s s s s s int frac address offset from drawbaseaddress s sign bit or sign extension 0 not used or 0 extension int integer or integer part of fixed point data frac fraction part of fixed point data sets color parameters for line drawing. these parameters are used in the gouraud shading mode. lrs r value at line draw start vertex lrde differential value of r element lgs g value at line draw start vertex lgde differential value of g element lbs b value at line draw start vertex lbde differential value of b element 7.1.8 pixel plot registers each register is used by the drawing commands. the registers cannot be accessed from the cpu or by using the setregister command. register address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 321 0 pxdc 0180h 0 0 00 int 0 pydc 0184h 0 0 00 int 0 pzdc 0188h 0 0 00 int 0 address offset from drawbaseaddress s sign bit or sign extension 0 not used or 0 extension int integer or integer part of fixed point data frac fraction part of fixed point data sets coordinate parameter for pixel plot. the foreground color is used. pxdc set x-coordinate position pydc set y-coordinate position pzdc set z-coordinate position 146 7.1.9 rectangle draw registers each register is used by the drawing commands. the registers cannot be accessed from the cpu or by using the setregister command. register address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rxs 0200h 0 0 0 0 int 0 rys 0204h 0 0 0 0 int 0 rsizex 0208h 0 0 0 0 int 0 rsizey 020ch 0 0 0 0 int 0 address offset from drawbaseaddress s sign bit or sign extension 0 not used or 0 extension int integer or integer part of fixed point data frac fraction part of fixed point data sets coordinate parameters for rectangle drawing. the foreground color is used. rxs set the x-coordinate of top left vertex rys set the y-coordinate of top left vertex rsizex set horizontal size rsizey set vertical size 147 7.1.10 blt registers each register is used by the drawing commands. the registers cannot be accessed from the cpu or by using the setregister command. register address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 saddr 0240h 0 0 0 0 0 0 0 address sstride 0244h 0 0 0 0 int 0 srxs 0248h 0 0 0 0 int 0 srys 024ch 0 0 0 0 int 0 daddr 0250h 0 0 0 0 0 0 0 address dstride 0254h 0 0 0 0 int 0 drxs 0258h 0 0 0 0 int 0 drys 025ch 0 0 0 0 int 0 brsizex 0260h 0 0 0 0 int 0 brsizey 0264h 0 0 0 0 int 0 address offset from drawbaseaddress s sign bit or sign extension 0 not used or 0 extension int integer or integer part of fixed point data frac fraction part of fixed point data sets parameters for blt operations saddr sets start address of source field in byte boundary. sstride sets horizontal size of source field srxs sets start x-coordinate position of source rectangle srys sets start y-coordinate position of source rectangle daddr sets start address of destination rectangle in byte boundary dstride sets horizontal size of destination field drxs sets start x-coordinate position of destination rectangle drys sets start y-coordinate position of destination rectangle brsizex sets horizontal size of rectangle brsizey sets vertical size of rectangle 148 7.1.11 fast2dline draw registers each register is used by the drawing commands. the registers cannot be accessed from the cpu or by using the setregister command. register address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lx0dc 0540h 0 0 0 0 int 0 ly0dc 0544h 0 0 0 0 int 0 lx1dc 0548h 0 0 0 0 int 0 ly1dc 054ch 0 0 0 0 int 0 address offset from drawbaseaddress s sign bit or sign extension 0 not used or 0 extension int integer or integer part of fixed point data frac fraction part of fixed point data sets coordinate parameters of both end points for fast2dline drawing lx0dc sets x-coordinate of vertex v0 ly0dc sets y-coordinate of vertex v0 lx1dc sets x-coordinate of vertex v1 ly1dc sets y-coordinate of vertex v1 149 7.1.12 fast2dtriangle draw registers each register is used by the drawing commands. the registers cannot be accessed from the cpu or by using the setregister command. register address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x0dc 0580h 0 0 0 0 int 0 y0dc 0584h 0 0 0 0 int 0 x1dc 0588h 0 0 0 0 int 0 y1dc 058ch 0 0 0 0 int 0 x2dc 0590h 0 0 0 0 int 0 y2dc 0594h 0 0 0 0 int 0 address offset from drawbaseaddress s sign bit or sign extension 0 not used or 0 extension int integer or integer part of fixed point data frac fraction part of fixed point data sets coordinate parameters of three vertices for fast2dtriangle drawing x0dc sets x-coordinate of vertex v0 y0dc sets y-coordinate of vertex v0 x1dc sets x-coordinate of vertex v1 y1dc sets y-coordinate of vertex v1 x2dc sets x-coordinate of vertex v2 y2dc sets y-coordinate of vertex v2 7.1.12 displaylist fifo registers dfifo (displaylist fifo) register address drawbaseaddress + 4a0h bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name dfifo r/w w default don t care fifo registers for displaylist transfer 150 8 timing diagram 8.1 host interface 8.1.1 cpu read/write timing diagram for sh3 mode t1: read/write start cycle (rdy in wait state) twh*: cycles inserted by hardware (rdy cancels the wait state as soon as the preparations are made.) t2: read/write end cycle (rdy ends in the wait state.) fig. 8.1 cpu read/write timing diagram for sh3 mode 9do l g'dwd 9do l g'dwd +l = +l = %&/. , $> @ cs %6 5' :(> @ '> @ :$, 7 t1 twh1 twh2 t2 '> @ { : xwait sampling in sh3 mode at read at write :dl w :dl w 1rw:dl w :dl w 7 7zk 7zk 7 151 8.1.2 cpu read/write timing diagram for sh4 mode t1: read/write start cycle (rdy is in the not-ready state.) twh*: cycles inserted by hardware (rdy asserts ready as soon as the preparations are made.) t2: read/write end cycle (rdy ends in the not-ready state.) fig. 8.2 cpu read/write timing diagram for sh4 mode valid data valid data +l = hi-z bclki a[24:2] cs bs rd xwe[3:0] d[31:0] rdy t1 twh1 twh2 t2 d[31:0] { : rdy sampling in sh4 mode at read at write notready notready ready notready t1 twh1 twh2 t2 152 8.1.3 cpu read/write timing diagram in v832 mode t1: read/write start cycle (ready is in the not-ready state.) twh*: cycles inserted by hardware (ready asserts ready as soon as the preparations are made.) t2: read/write end cycle (ready is in the not-ready state.) ready is placed in the ready state and then set to hi-z. note: the xxben signal is used only when performing a write from the cpu; it is not used when performing a read from the cpu. fig. 8.3 cpu read/write timing diagram in v832 mode mwr(iowr) valid data valid data hi-z hi-z bcyst a[23:2] cs bs mrd(iord xxben[3:0] d[31:0] ready d[31:0] { : ready sampling in v832 mode at read at write not-read y not-read y not-read y ready ready t1 twh1 twh2 t2 153 8.1.4 sh4 single-address dma write (transfer of 1 long word) { : dreq sampling and channel priority determination for sh mode (dreq = level detection) *1: in the cycle steal mode, even when dreq is already asserted at the 2nd dreq sampling, the right to use the bus is returned to the cpu once. in the burst mode, dmac secures the right to use the bus unless dreq is negated. fig. 8.4 sh4 single-address dma write (transfer of 1 long word) the MB86290A writes data according to the dtack assert timing. when data cannot be received, the dreq signal is automatically negated. and then the dreq signal is reasserted as soon as data becomes ready to be received. dmac cpu *1 dmac cpu *1 bclkin d[31:0] dreq drack dtack acceptance acceptance acceptance bus cycle 154 8.1.5 sh4 single-address dma write (transfer of 8 long words) { : dreq sampling and channel priority determination for sh mode (dreq = level detection) *1: in the cycle steal mode, even when dreq is already asserted at the 2nd dreq sampling, the right to use the bus is returned to the cpu once. in the burst mode, dmac secures the right to use the bus unless dreq is negated. fig. 8.5 sh4 single-address dma write (transfer of 8 long words) the MB86290A writes data in accordance with the dtack assert timing. when data cannot be received, the dreq signal is negated automatically. and then the dreq signal is reasserted as soon as data becomes ready to be received. 1st dmac cpu cpu *1 bclkin d[31:0] dreq drack dtack acceptance bus cycle acceptance 155 8.1.6 sh3/4 dual-address dma (transfer of 1 long word) for the MB86290A, the read/write operation is performed according to the sram protocol. fig. 8.6 sh3/4 dual-address dma (transfer of 1 long word) in the dual-address mode, the dreq signal is kept asserted until the transfer ends by default. consequently, to negate the dreq signal when the MB86290A cannot return the ready signal immediately, set the dbm register. bclkin d[31:0] a[24:2] read destination address write source address dreq destination address source address read write 156 8.1.7 sh3/4 dual-address dma (transfer of 8 long words) for the MB86290A, the read/write operation is performed according to the sram protocol. fig. 8.7 sh3/4 dual-address dma (transfer of 8 long words) in the dual-address mode, the dreq signal is kept asserted until the transfer ends by default. consequently, to negate the dreq signal when the MB86290A cannot return the ready signal immediately, set the dbm register. bclkin d[31:0] a[24:2] read 1 source address ?c ?c ?c ?c ?c ?c ?c ?c ?c ?c ?c ?c destination address ?c ?c ?c ?c ?c ?c dreq read 2 read 8 write 1 write 2 write 8 157 8.1.8 v832 dma transfer for the MB86290A, the read/write operation is performed according to the sram protocol. fig. 8.8 v832 dma transfer during dma transfer, the dreq signal is kept asserted until the transfer ends by default. consequently, to negate the dreq signal when the MB86290A cannot return the ready signal immediately, set the dbm register. bclkin d[31:0] a[23:2] dmarq dmaak read destination address write source address destination address source address read write 158 8.1.9 sh4 single-address dma transfer end timing { : dreq sampling and channel priority determination for sh mode (dreq = level detection) fig. 8.9 sh4 single-address dma transfer end timing dreq is negated three cycles after drack is written as the last data. bclkin d[31:0] dreq drack dtack acceptance last data acceptance 159 8.1.10 sh3/4 dual-address dma transfer end timing for the MB86290A, the read/write operation is performed according to the sram protocol. fig. 8.10 sh3/4 dual-address dma transfer end timing dreq is negated three cycles after drack is written as the last data. bclkin d[31:0] a[24:2] read destination address source address dreq drack dtack write 160 8.1.11 v832 dma transfer end timing for the MB86290A, the read/write operation is performed according to the sram protocol. fig. 8.11 v832 dma transfer end timing dmmak and xtc are anded inside the MB86290A to end dma. bclkin d[31:0] a[24:2] dmarq dmaak xtc read destination address write source address 161 8.2 graphics memory interface the access timing for the MB86290A and the graphics memory is explained. 8.2.1 timing of read access to same row address fig. 8.2.1 timing of read access to same row address this timing diagram shows that the same row address of sdram is read- accessed four times from the MB86290A. the read command is issued after trcd has elapsed after the actv command was issued. data that is output after cl has elapsed after the read command was issued is written to the MB86290A. mclko cl trcd ma mwe mcas mras md row col data data data data col col col row: row address col: column address data: read data trcd: ras to cas delay time cl: cas latency dqm note: this timing is used when cl2 is operating. 162 8.2.2 timing of read access to different row addresses fig. 8.2.1 timing of read access to different row addresses this timing diagram shows that different row addresses of sdram are read- accessed from the MB86290A. an sdram page boundary is located between the address to be read first and the address to be read next. consequently, the precharge command is issued at the timing that meets the tras condition, and then after trp has elapsed, the actv command is reissued and the read command is issued. row: row address col: column address data: read data tras: ras active time trcd: ras to cas delay time cl: cas latency trp ?f ras precharge time mclko tras cl trcd ma mwe mcas mras md row col d ata trp row col trcd cl data dqm note: this timing is used when cl2 is operating. 163 8.2.3 timing of write access to same row address fig. 8.2.3 timing of write access to same row address this timing diagram shows that the same row address of sdram is write- accessed four times from MB86290A. the write command is issued after trcd has elapsed after the actv command is issued. then, data is written to sdram. mclko trcd ma mwe mcas mras md row col data data data data col col col row: row address col: column address data: read data trcd: ras to cas delay time dqm 164 8.2.4 timing of write access to different row addresses fig. 8.2.4 timing of write access to different row addresses this timing diagram shows that different row addresses of sdram are write- accessed from the MB86290A. an sdram page boundary is located between the address to be written to first and the address to be written to next. consequently, the precharge command is issued at the timing that meets the tras condition, and then after trp has elapsed, the actv command is reissued and the read command is issued. row: row address col: column address data: read data tras: ras active time trcd: ras to cas delay time trp: ras precharge time mclko tras trcd ma mwe mcas mras md row col data trp row col trcd data dqm 165 8.2.5 timing of read/write access to same row address fig. 8.2.5 timing of read/write access to same row address this timing diagram shows that a row address of sdram is read-accessed from the MB86290A, and then immediately afterwards the same row address is write-accessed from the MB86290A. the write command is issued after lowd has elapsed after read data is output from sdram. row: row address col: column address data: read data tras: ras active time trcd: ras to cas delay time cl: cas latency trp: ras precharge time lowd: last output to write command delay mclko cl trcd ma mwe mcas mras md row col data data dqm lowd col note: this timing is used when cl2 is operating. 166 8.2.6 delay between actv commands fig. 8.2.6 delay between actv commands the actv command is issued to the sdram row address from the MB86290A after trrd has elapsed after the previous actv command is issued. row: row address trrd: ras to ras bank active dela y time mclko ma mwe mcas mras row row trrd 167 8.2.7 delay between refresh command and next actv command fig. 8.2.7 delay between refresh command and next actv command the actv command is issued after trc has elapsed after the refresh command is issued. row: row address trc: ras c y cle time mclko ma mwe mcas mras row trc 168 8.3 display timing 8.3.1 non-interlaced video mode in the above diagram, vtr, hdp, etc., are the settings of their associated registers. the vsync/frame interrupt is asserted when display of the last raster ends. when updating display parameters, synchronize with the frame interrupt so no display disturbance occurs. calculation for the next frame is started immediately after the vertical synchronization pulse is asserted, so the parameters must be updated by the time that calculation is started. vdp+1 rasters vsync hsync vsp+1 rasters vtr+1 rasters vsw+1 rasters hdp+1 clocks hsp+1 clocks htp+1 clocks hsw+1 clocks hsync aoutx aoutx assert frame interrupt assert vsync interrupt 169 8.3.2 interlaced video mode in the above diagram, vtr, hdp, etc., are the settings of their associated registers. aoutx vdp+1 rasters vsync hsync vsp+1 rasters vtr+1 rasters (odd field) vsw+1 rasters vtr+1 rasters (even field) eo(out) vsw+1 rasters vsync hsync eo(out) vdp+1 rasters vsp+1 rasters aoutx assert vsync interrupt assert vsync interrupt assert frame interrupt 170 cautions 8.4 cpu cautions (1) enable the hardware wait for the areas to which the MB86290A is linked. set the software wait count to 1. (2) when starting dma by issuing an external request, do so after setting the transfer count register (dtcr) and mode setting register (dsur) of the MB86290A to the same value as the cpu setting. in the v832 mode, there is no need to set dtcr. (3) when MB86290A is read-/write-accessed from the cpu during dma transfer, do not access the registers and memories related to dma transfer. if these registers and memories are accessed, reading and writing of the correct value is not assured. (4) in the sh mode, only the lowers 32 mbytes are used (a[25] is not used), so do not access the uppers 32 mbytes. when linking other devices to the uppers 32 mbytes, create chip select for the MB86290A by using glue logic. (5) set dreq (dmarq) to detection. (6) set the sh-mode dack/drack to high active output, v832-mode dmaak to high active, and v832-mode tc to low active. 8.5 sh3 mode (1) when the rdy pin is low, it is in the wait state. (2) dma transfer in the single-address mode is not supported. (3) dma transfer in the dual-address mode supports the direct address transfer mode, but does not support the indirect address transfer mode. (4) 16-byte dma transfer in the dual-address mode is not supported. (5) the int signal is low active. 172 8.6 sh4 mode (1) when the rdy pin is low, it is in the ready state. (2) at dma transfer in the single-address mode, transfer from the main memory (sh-mode memory) to fifo of the MB86290A can be performed, but transfer from the MB86290A to the main memory cannot be performed. (3) dma transfer in the single-address mode is performed in units of 32 bits or 32 bytes. (4) sh4-mode 32-byte dma transfer in the dual-address mode supports inter-memory transfer, but does not support transfer from memory to fifo. (5) the int signal is low active. 8.7 v832 mode (1) when the rdy pin is low, it is in the ready state. (2) set the active level of dmaak to high-active in v832 mode. (3) dma transfer supports the single transfer mode and demand transfer mode. (4) the int signal is high-active. set the v832-mode registers to high-level trigger. 8.8 dma transfer modes supported by sh3, sh4, and v832 table 8-1 table of dma transfer modes supported by sh3, sh4, and v832 single-address mode dual-address mode sh3 sh 3 does not support the single- address mode. sh3 supports the direct address transfer mode; it does not support the indirect address transfer mode. transfer is performed in 32-bit units. sh3 supports the cycle steal mode and burst mode. sh4 transfer is performed in units of 32 bits or 32 bytes. sh4 supports the cycle steal mode and burst mode. transfer is performed in 32-bit units. transfer to memory is performed in 32-byte units. sh4 supports transfer to fifo. sh4 supports the cycle steal mode and burst mode. v832 transfer is performed in 32-bit units. v832 supports the single transfer mode and demand transfer mode. 173 9 electrical characteristics (preliminary target specifications) 9.1 absolute maximum ratings maximum ratings parameter symbol maximum rating unit supply voltage vddl *1 vddh -0.5 < vddl < 3.0 -0.5 < vddh < 4.0 v input voltage vi viv *2 -0.5 < vi < vddh+0.5 (<4.0) -0.5 < vi < vddh+4.0 (<6.0) v output current io +13 / -13 ma power current ipow 60 ma ambient temperature top 0 < top < 70 (-40 < top < 85) *3 c storage temperature tst -55 < tst < +125 c *1 includes analog power supply and pll power supply *2 hsync, vsync, eo input *3 temperature extended version 173 9.2 recommended operating conditions 9.2.1 recommended operating conditions recommended operating conditions specifications parameter symbol min. typ. max. unit supply voltage vddl *1 vddh 2.3 3.0 2.5 3.3 2.7 3.6 v input high voltage vih vihv *2 2.0 2.0 vddh+0.3 5.5 v input low voltage vil vilv *2 -0.3 -0.3 0.8 0.8 v input voltage to vref vref 1.05 1.10 1.15 v vro external resistance rvro 2.7 k? aout external resistance *3 raout 75 ? acomp external capacitance *4 cacomp 0.1 f ambient temperature top 0 70 c *1 includes analog power supply and pll power supply *2 hsync, vsync, eo input *3 aoutr, aoutg, aoutb pins *4 acompr, acompg, acompb pins specifications parameter symbol min. typ. max. unit supply voltage vddl *1 vddh 2.6 3.5 2.5 3.3 2.7 3.6 v ambient temperature ta - 40 7.0 c others t 9.2.2 power-on precautions there is no restriction on the order of power-on/power-off between vddl and vddh. however, do not supply only vddh for more than a few seconds. do not supply hsync, vsync and ec signals while the voltage supply is off. (see the recommended input voltage in the section on absolute maximum ratings.) after power-on, hold the s input at the l level for at least 500 ns. then, after setting the s-input to the h level, hold the xreset input at the l level for at least 300 s. 174 9.3 dc characteristics condition: vddl = 2.5 ? 0.2 v, vddh = 3.3 ? 0.3 v, vss = 0.0 v, ta = 0- 70 ? c specifications parameter symbol min. typ. max. unit output high voltage *1 voh vddh- 0.2 vddh v output low voltage *2 vol 0.0 0.2 v output high current ioh1 *3 ioh2 *4 ioh3 *5 -2.0 -4.0 -8.0 ma output low current iol1 *3 iol2 *4 iol3 *5 2.0 4.0 8.0 ma aout output current *6 full scale zero scale iaout 9.90 0 10.42 2 10.94 20 ma a aout voltage *7 vaout -0.1 1.1 v input leakage current il +5/-5 a load capacitance c 16 pf *1 ioh = -100 a *2 iol = 100 a *3 output current of md0-63, mdqm0-7 *4 output current of all signals except *3 and *5 (not including analog signals) *5 output current of mclko *6 output current of aoutr, aoutg and aoutb (vref = 1.10 v, rvro = 2.7 k ? ) (the formula for full-scale output current calculation is (vref/rvro) x 25.575.) *7 aoutr, aoutg and aoutb pins 175 9.4 ac characteristics 9.4.1 host interface clock specifications parameter symbol condition min. typ. max. unit bclki frequency f bclki 100 mhz bclki h-width t hbclki 1ns bclki l-width t lbclki 1ns host interface signals specifications parameter symbol condition min. typ. max. unit address set up time t ads 3.0 ns address hold time t adh 1.0 ns bs set up time t bss 3.5 ns bs hold time t bsh 0.0 ns cs set up time t css 3.5 ns cs hold time t csh 0.0 ns rd set up time t rds 3.0 ns rd hold time t rdh 1.0 ns we set up time t wes 3.0 ns we hold time t weh 1.0 ns write data set up time t wds 5.0 ns write data hold time t wdh 1.0 ns dtack set up time t daks 3.0 ns dtack hold time t dakh 1.0 ns drack set up time t drks 3.0 ns drack hold time t drkh 1.0 ns read data delay time (for xrd) t rddz 4.0 8.5 ns read data delay time t rdd 4.0 9.5 ns rdy delay time (for xcs) sh t rdydz 3.0 9.0 ns rdy delay time (for xcs) v832 t rdydz 3.0 8.5 ns rdy delay time t rdyd 3.5 7 ns int delay time t intd -10ns dreq delay time t dqrd 3.5 7 ns mode hold time t modh *1 20 ns *1 hold time requirement for reset release 176 9.4.2 video interface clock specifications parameter symbol condition min. typ. max. unit clk frequency f clk 14.32 mhz clk h-width t hclk 25 ns clk l-width t lclk 25 ns dclki frequency f dclki 67 mhz dclki h-width t hdclki 5ns dclki l-width t ldclki 5ns dclko frequency f dclko 67 mhz input signals specifications parameter symbol condition min. typ. max. unit t whsync0 *1 3 clock hsync input pulse width t whsync1 *2 3 clock hsync input set up time t shsync *2 10 ns hsync input hold time t hhsync *2 10 ns vsync input pulse width t whsync1 1 hsync period eo input set up time t seo *3 10 ns eo input hold time t heo *3 10 ns *1 in pll synchronization mode (cks = 0), base clock output from internal pll (period = 1/14*fclk) *2 in dclki synchronization mode (cks = 1), base clock = dclki *3 for vsync negation edge output signals specifications parameter symbol condition min. typ. max. unit eo output delay time t deo *4 10 ns hsync output delay time t dhsync 10 ns vsync output delay time t dvsync 10 ns csync output delay time t dcsync 10 ns gv output delay time t dgv 10 ns *4 eo output changes at timing of vsync assertion 177 9.4.3 graphics memory interface clock specifications parameter symbol condition min. typ. max. unit mclko frequency t mclko 100 ns mclko h-pulse width t hmclko 1ns mclko l-pulse width t lmclko 1ns mclki delay t dmclki 100 mhz mclki h-frequency t hmclki 1ns mclki h-pulse width t lmclki 1ns t oid 14ns input/output signals specifications parameter symbol condition min. typ. max. unit ma, mras, mcas, mwe, cke setup time t mads *1 3.5 ns ma, mras, mcas, mwe, cke hold time t madh *1 1 ns mdqm data setup time t mdqmds *1 3.5 ns mdqm data hold time t mdqmdh *1 1 ns md output data setup time t mdods *1 3.5 ns md output data hold time t mdodh *1 1 ns md input data setup time t mdids *2 3 ns md input data hold time t mdidh *2 1 ns *1: setup hold time for mclko *2: setup hold time for mclki 9.4.4 pll specifications parameter specifications description input frequency (typ.) 14.31818 mhz output frequency 200.45452 mhz x 14 duty ratio 101.3~93.1% h/l pulse width ratio of pll output jitter 180~-150ps frequency tolerant of two consecutive clock cycles 178 9.5 timing diagram 9.5.1 host interface clock input signal setup/hold times bclki 1/f bclki t lbclki t hbclki bclki t ads, t bss, t css, t rds, t wes, t wds, t daks, t drk a, bs, cs, rd, we, d, dtack, drack t adh, t bsh, t csh, t rdh, t weh, t wdh, t dakh, t drk 179 dreq out put delay times rdy delay (for cs) bclki t drqd, t intd dreq (output) hi-z bclki t rdydz rdy (output) t rdydz cs hi-z 180 rdy, d output delay mode signal hold time bclki d (output) t rddz rd hi-z rdy t rdyd t rdyd t rdd output data reset t modh mode 181 9.5.2 video interface clock hsync signal setup/hold eo signal setup/hold clk 1/f clk t lclk t hclk v ih v il dclki t hdclki t ldclki 1/f dclki t shsync t hhsync hsync (input) vsync t seo t heo eo (input) 182 output signal delay dclko t deo , t dhsync, t dvsync , t dcsync, t dgv eo (output) hsync (output) vsync (output) csync gv 183 9.5.3 graphics memory interface clock input signal setup/hold times mclko t mclko t lmclko t hmclko mclki t smd md0-63 t hmd 184 mclki signal delay output signal delay mclko t dmclki mclki mclko t mads, t mdods, t mdqmds ma, mras, mcas, mwe, cke, md, mdqm t madh, t mdodh, t mdqmdh |
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